Methods and apparatus for testing integrated circuits

Details Methods and apparatus for testing integrated circuits Methods and apparatus for testing integrated circuits

1999-08-03

2003-05-06

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S538000

Reexamination Certificate

active

06560735

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods and apparatus for testing semiconductor integrated circuits (IC) devices, and more specifically to testers for solder bump IC devices.
BACKGROUND OF THE INVENTION
Testing of semiconductor devices is typically conducted with apparatus constructed on the “bed of nails” principle. This type of test equipment is highly developed and widely used. However, as the pitch of IC devices shrinks, it becomes difficult to reliably access the contact pads on the IC device. The difficulty is not only accessing a small array of contacts, but the contact resistance varies significantly from pin to pin, and is sometimes excessive. Improvements in test equipment for solder bump arrays have been made. One example is the use of a silicon test bed in which a pattern of recesses is etched into a silicon wafer, and each recess is interconnected to a test circuit that simulates the device circuit. The array of recesses is matched to the solder ball array on the IC device. The use of silicon as the test bed offers the advantages of high planarity, thermal properties that match the IC substrate, notably coefficient of thermal expansion, and the availability of a well developed interconnect technology for fabricating the test circuit.
In spite of this advance, further improvements IC testing apparatus are continually being sought. In particular, improving the reliability of electrical contact over the large array of solder bumps is a primary goal. Although the bump arrays in state of the art solder bump devices are relatively uniform, small variations in bump size and bump height are typical. Small variations in the etched recesses also occur. As a result, all of the bumps do not effectively contact the recesses in the test array when the IC chip is aligned to the array. It is necessary to apply a large axial force to the IC chip to cause the bump or bumps in the “high” spots of the bump array to deform sufficiently so that the bumps in the low spots adequately contact the test array. The force required to effect this, even in high precision advanced IC packages, is frequently near the breaking point of the IC substrate. This is a special concern for testing devices at the wafer level, where high stress on the wafer may cause fracture or other problems.
STATEMENT OF THE INVENTION
We have developed a test apparatus for either singulated IC devices or wafers that greatly reduces the pressure required to bring all bumps in the IC array into contact with the test array. The test apparatus of the invention has a flat test bed with an array of sockets arranged to receive the array of IC solder balls, and the sockets in the flat test bed test are provided with re-entrant sidewalls so that, in contrast with the flat or dished shape surfaces of prior art recesses, the sockets have sharp edges that contact the solder bump array. As a result the deformation required to bring all solder bumps in the array into firm contact with the test array surfaces is sharply reduced, and the force required to effect the deformation is correspondingly reduced. In the preferred embodiments the re-entrant features in the sockets are formed by intersecting grooves in the surface of the flat bed. When pairs of parallel V-grooves are used, and the grooves made to overlap, then one or more pyramids form at the intersections of pairs of grooves. The point of the pyramid at the bottom of the socket becomes a main bearing feature to provide reliable electrical contact.


REFERENCES:
patent: 4288808 (1981-09-01), Hantusch
patent: 5479105 (1995-12-01), Kim et al.
patent: 5523696 (1996-06-01), Charlton et al.
patent: 5528159 (1996-06-01), Charlton et al.
patent: 5568057 (1996-10-01), Kim et al.
patent: 5581195 (1996-12-01), Lee et al.
patent: 5880590 (1999-03-01), Desai et al.
patent: 5940680 (1999-08-01), Lee et al.
patent: 5983492 (1999-11-01), Fjelstad
patent: 5990692 (1999-11-01), Jeong et al.
patent: 6037786 (2000-03-01), Palagonia
patent: 6188231 (2001-02-01), Palagonia
patent: 6229320 (2001-05-01), Haseyama et al.
patent: 6262581 (2001-07-01), Han

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