Method to verify the performance of BIST circuitry for...

Details Method to verify the performance of BIST circuitry for... Method to verify the performance of BIST circuitry for...

2005-09-06

2005-09-06

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C703S015000

Reexamination Certificate

active

06941499

ABSTRACT:
A new method and apparatus to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device is achieved. A set of faults is introduced into an embedded memory behavior model. The embedded memory behavior model comprises a high-level language model. Each member of the set of faults comprises a finite state machine state, a memory address, and a memory data fault. The built-in self-test circuit and the embedded memory behavior model are then simulated. The built-in self-test circuit generates input data and address patterns for the embedded memory behavior model. The embedded memory behavior model outputs memory address and data in response to the input data and address patterns. The input address and data and the memory address and data are compared in the built-in self-test circuit and a fault output is generated if not matching. The fault output and the set of faults are compared to verify the performance of the built-in self-test circuit.

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J. Dreibelbis et al., “Processor-Based Built-In Self-Test for Embedded DRAM”, IEEE Journal of Solid-State Circuits, vol. 33, No. 11, Nov. 1998, pp 1731-1740.
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