Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-09-10
1999-09-07
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438266, H01L 21336
Patent
active
059500875
ABSTRACT:
A method is provided for forming a common self-aligned source line in order to reduce the number of surface contacts and at the same time alleviate the field oxide encroachment into the cell area. Thus, the size of the split-gate flash memory is substantially reduced on both accounts. This is accomplished by forming a buffer polysilicon layer over the floating gate to serve as an etch stop to protect the first poly-oxide of the floating gate during the self-aligned source etching.
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Hsieh Chia-Ta
Kuo Di-Son
Lin Yai-Fen
Peng Kuo-Reay
Sung Hung-Cheng
Ackerman Stephen B.
Chaudhari Chandra
Chen Jack
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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