Method of planarizing non-volatile memory device

Details Method of planarizing non-volatile memory device Method of planarizing non-volatile memory device

2002-07-25

2003-11-18

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S697000

Reexamination Certificate

active

06649471

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of planarizing to remove a difference in height between a flash memory cell area and a logic device peripheral circuit area when forming a wordline of a non-volatile memory device in which a flash memory device and a logic device are merged.
2. Description of the Related Art
Semiconductor memory devices include RAM devices and ROM devices. In the RAM device, such as a DRAM (dynamic random access memory) and an SRAM (static random access memory), data are rapidly inputted/outputted into/from the RAM device and are volatilized as the lapse of time. On the contrary, the ROM device constantly maintains inputted data, but data are slowly inputted/outputted into/from the ROM device. Among those ROM devices, an EEPROM (electrically erasable and programmable ROM) capable of electrically inputting/outputting data and a flash memory device are widely used.
Further, conventionally, multiple semiconductor devices having different functions are merged in one chip due to the characteristics of manufacturers and demand on the users, thereby enhancing added value. For typical examples, there are a merged DRAM & logic (MDL) device including DRAM cells and logic devices and a merged flash & logic (MFL) device including flash memory cells and logic devices.
Generally, the programming of the flash memory cell is carried out by hot-electron injection into the floating gate. That is, an applied positive voltage on a control gate is coupled to a floating gate, so that electrons are captured in the floating gate through a tunnel oxide layer from a substrate. On the contrary, the erasing mechanism of the flash memory cell is Fowler-Nordheim (hereinafter, referred to as “F-N”) tunneling off the floating gate to the drain region. That is, the electrons in the floating gate are transferred to the substrate by applying a negative voltage on the control gate. When a program is being executed, the ratio of coupled voltage on the floating gate due to the applied voltage on the control gate is the coupling ratio. As the coupling ratio becomes higher, the speed and performance of the device are enhanced.
In case of the MFL device, as the design rule decreases to less than 0.18 &mgr;m, a split-gate structure in which a tip is formed on the edge area of the floating gate is used to increase the coupling ratio of the flash memory cell. By doing so, the erase efficiency and the program efficiency are improved to increase the coupling ratio.
In the flash memory cell with the split-gate structure, a wordline is formed using a conventional chemical mechanical polishing (hereinafter, referred to as “CMP) process. So the whole chip should be planarized to uniformly form the wordline in a subsequent gate patterning process.
FIGS. 1A
to
7
B are sectional views illustrating a conventional method of forming a wordline in the split-gate type MFL device. Here,
FIGS. 1A
,
2
A,
3
A,
4
A,
5
A,
6
A and
7
A show a cell area in which a flash memory device is formed, and
FIGS. 1B
,
2
B,
3
B,
4
B,
5
B,
6
B and
7
B show a peripheral circuit area in which a logic device is formed.
Referring to
FIGS. 1A and 1B
, a first oxide layer
11
for forming a gate oxide layer (i.e., a tunnel oxide layer) of the flash memory device, a first polysilicon layer
13
for forming a floating gate and a nitride layer (not shown) are sequentially formed on a semiconductor substrate
10
such as a silicon substrate. Then, the nitride layer is patterned through a photolithography process to form a nitride layer pattern
16
defining a floating gate region. An oxide layer (not shown) is deposited on the nitride layer pattern
16
and the first polysilicon layer
13
, and etched back to form spacers
18
on the sidewalls of the nitride layer pattern
16
.
Using the spacer
18
as an etching mask, the first polysilicon layer
13
and the first oxide layer
11
are etched away. Through a typical ion-implantation process, a source region
20
is formed in the surface portion of the exposed substrate between the spacers
18
. Then, after performing an oxidation process to cure silicon damage caused by the described etching process, a liner oxide layer (not shown) is deposited on the resultant structure and etched back to insulate the first polysilicon layer
13
from a source line that is to be formed in a subsequent process.
Referring to
FIGS. 2A and 2B
, a second polysilicon layer
21
is deposited on the resultant structure and planarized by a CMP or an etch-back process until the surface of the nitride layer pattern
16
is exposed. By doing so, the source line
22
connected to the source region
20
is formed so as to fill a gap between the spacers
18
.
Referring to
FIGS. 3A and 3B
, after removing the nitride layer pattern
16
by a phosphoric acid stripping process, the first polysilicon layer
13
is dry-etched away using the spacers
18
as an etching mask. Then, after performing an oxidation process to cure silicon damage caused by the described etching process, the substrate is cleaned using HF. As a result, there is formed a floating gate structure
40
of the flash memory device including a gate oxide layer
12
, two floating gates
14
separated by the spacers
18
and the source line
22
filling the gap between the spacers
18
.
Referring to
FIGS. 4A and 4B
, a second oxide layer
23
, a third polysilicon layer
25
for forming the wordline and the gate and a nitride layer
27
are sequentially formed on the entire surface of the substrate
10
including the floating gate structure
40
. The second oxide layer
23
serves as a dielectric interlayer for insulating the floating gate from a control gate on the memory cell area and serves as a gate oxide layer of the logic device on the peripheral circuit area.
Referring to
FIGS. 5A and 5B
, the nitride layer
27
is removed by a CMP process until the surface of the floating gate structure
40
, preferably the source line
22
is exposed, thereby planarizing the cell area and the peripheral circuit area. At this time, a nitride layer residue
28
remains on the part of the low step height.
Referring to
FIGS. 6A and 6B
, after selectively oxidizing the exposed surface of the third polysilicon layer
25
and the source line
22
to form an oxide layer
30
, the nitride layer residue
28
is removed by a wet etching process. Then, through a photo process, a photoresist pattern
32
is formed to mask the cell area and to open a gate region of the peripheral circuit area.
Referring to
FIGS. 7A and 7B
, using the oxide layer
30
of the cell area and the photoresist pattern
32
of the peripheral circuit area as an etching mask, the exposed third polysilicon layer
25
is dry-etched away. By doing so, the wordline (i.e., the control gate)
26
a
of the flash memory device and the gate
26
b
of the logic device, which have a vertical profile, are simultaneously formed. Here, reference numeral
24
a
indicates the dielectric interlayer for insulating the control gate
26
a
from the floating gate
14
and reference numeral
24
b
indicates a gate oxide layer of the logic device.
At this time, the oxide layer
30
used as the etching mask is almost consumed during etching the third polysilicon layer
25
and is removed completely in a subsequent cleaning process and a pre-cleaning process for silicidation.
According to the described conventional method, since the basic height difference between the cell area and the peripheral circuit area exists already before performing the CMP process of
FIG. 5
, the CMP process should be sufficiently carried out to remove this step height. Therefore, due to the peripheral circuit area of the low height, the nitride layer
71
is removed completely on the edge of the cell area and the peripheral circuit area by the excessive CMP process, so that the formation of the wordline and the gate becomes impossible.
Further, when the wordline
26
a
is formed

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