Method of patterning narrow gate electrode

Details Method of patterning narrow gate electrode Method of patterning narrow gate electrode

1999-11-19

2001-01-16

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S736000, C438S738000

Reexamination Certificate

active

06174818

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of photolithographic etching with particular reference to the formation of narrow lines such as FET gates.
BACKGROUND OF THE INVENTION
Silicon integrated circuits continue to grow ever denser, requiring that the gate oxides in FETs (field effect transistors) be thinner and, in particular, that the gate electrodes in the FETs become narrower. Said gate electrodes are most usually made of polysilicon and, until relatively recently, were patterned by conventional use of photoresist masking.
However, as gates have grown narrower, use of a photoresist mask has become increasingly problematical. There are a number of reasons for this—undercutting of the photoresist during etching, which can be tolerated in wider lines, introduces a degree of uncertainty into the process which can no longer be tolerated in very narrow lines; because of the high level of resolution required, the photoresist layer must be thinner than that used for etching wider lines; sensitivity of photoresist-based processes to process parameters such as exposure wavelength, brand of resist used, etc. becomes more of a problem; and line width control, and reduction of line edge roughness, through use of photoresist trimming, becomes more difficult if the photoresist is also used as the primary etch mask.
Another factor that needs to be considered when forming structures through etching is the need to use an ARC (anti-reflection coating). This is laid down just below the photoresist layer to prevent formation of standing wave patterns within the resist. ARCs may be either organic or inorganic, the former being relatively thick while the latter are relatively thin. For reasons that will become apparent, an inorganic ARC is part of the present invention.
A routine search of the prior art was performed but no references that describe the exact process taught by the present invention were discovered. Several references of interest were, however, encountered. For example, Bell (U.S. Pat. No. 5,767,018) determined that a process being used by him to etch a silicon oxynitride ARC caused pitting of the polysilicon gate structure. Polymer formation during etching was considered to be a large contributor to this problem so an etchant that did not form a polymer was selected. This allowed a passivating coating to form on the sidewalls as the polysilicon was etched (using HBr/Cl
2
/He—O
2
). The final step was an anisotropic etch that cleaned the top surface of the gate without removing the protective layer from the sidewalls.
Kumar et al. (U.S. Pat. No. 5,851,926) teach use of a tungsten silicide hard mask together with an NF
3
and Cl
2
etch to achieve vertical edges for a polysilicon gate. Keller (U.S. Pat. No. 5,346,586) etches a polysilicon layer that has been coated with a silicide layer by first forming an oxide hard mask and then successively etching the suicide and polysilicon layers.
Muller (U.S. Pat. No. 5,674,409) shows a photoresist trim process for forming lines while Shin et al. (U.S. pat. No. 5,914,276) describe a process for etching a polycide/polysilicon gate.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for forming a very narrow line through photolithography and etching.
Another object has been that said process be optimized for the formation of a gate electrode of polysilicon for a field effect transistor.
A further object has been that said process be compatible with photoresist trimming and photo rework.
These objects have been achieved by using a hard mask of silicon oxynitride covered by a thin layer of silicon oxide during the etching of the polysilicon to form the gate. The thicknesses of the two layers that make up the hard mask are chosen so that the structure also serves as an ARC for the photoresist coating immediately above it. A relatively thin layer of the latter is used in order to improve resolution. After the photoresist has been patterned it may be trimmed or it may be removed and re-formed, with the silicon oxide layer providing protection for the underlying silicon oxynitride. After the hard mask has been formed, all photoresist is removed and the polysilicon is etched. This also leads to removal of the silicon oxide layer and part of the silicon oxynitride as well.


REFERENCES:
patent: 5345586 (1994-09-01), Keller
patent: 5346586 (1994-09-01), Keller
patent: 5512506 (1996-04-01), Chang et al.
patent: 5674409 (1997-10-01), Muller
patent: 5762714 (1998-06-01), Mohn et al.
patent: 5767018 (1998-06-01), Bell
patent: 5851926 (1998-12-01), Kumar et al.
patent: 5914270 (1999-06-01), Coutos-Thevenot et al.
patent: 5914276 (1999-06-01), Shin et al.
patent: 6008135 (1999-12-01), Oh et al.
patent: 6013574 (2000-01-01), Hause et al.

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