Method of manufacture of CMOS device using additional...

Details Method of manufacture of CMOS device using additional... Method of manufacture of CMOS device using additional...

1998-02-27

2001-01-09

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S223000, C438S224000, C438S309000, C438S358000, C438S542000

Reexamination Certificate

active

06171891

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to CMOS devices with enhanced ESD performance.
2. Description of Related Art
Junction leakage and junction short circuits to the substrate are more and more likely to occur in advanced technology devices as the dimensions of the devices forming those circuits become smaller and smaller.
U.S. Pat. No. 5,514,611 of Kim et al. for “Method for Manufacturing a Semiconductor Memory Device Having a Read-Only Memory Cell” shows a S/D (source/drain) structure with three I/I (Ion Implanted) doped regions.
U.S. Pat. No. 5,559,352 of Hsue for “ESD Protection Improvement” shows an ESD circuit with three I/I doped regions.
U.S. Pat. No. 5,493,142 of Randazzo et al. for “Input/Output Transistors with Optimized ESD Protection” has a lightly doped region disposed near the gate and the surface of the substrate. A sidewall oxide layer is selectively etched to extend laterally from a gate by a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may extend laterally an appreciable amount in that direction. Heavily doped S/D regions are implanted in the substrate. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.
U.S. Pat. No. 5,130,760 of Matzen et al. for “Bidirectional Surge Suppressor Zener Diode Circuit With Guard Ring” describes a semiconductor device incorporating doped regions of a substrate and epitaxial layers which result in a dual Zener diode arrangement having the Zener diodes associated in an opposite polarity arrangement.
SUMMARY OF THE INVENTION
A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate electrode layer patterned into gate electrode stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped source/drain regions in the N-well. Form N− lightly doped source/drain regions in the P-well. Form spacers on the sidewalls of the gate electrode stacks. Thereafter form deep N− lightly doped source/drain regions in the P-well, and form deep P− lightly doped source/drain regions in the N-well. Form heavily doped P++ regions self-aligned with the gate electrode below future P+ source/drain sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate electrode below future N+ source/drain sites to be formed self-aligned with the spacers in the P-well.
Form the N+ type source/drain regions in the P-well in the source/drain sites. Form the P+ type source/drain regions in the N-well in the source/drain sites. Form refractory metal silicide layers over the gate electrode layers.
Form refractory metal silicide layers over the source/drain regions, form P−/N++ junctions below the N+ source/drain regions in the P-well, and form N−/P++ junctions below the P+ source/drain regions in the N-well.
The deep lightly doped N− and P− regions are formed to a depth from about 0.2 &mgr;m to about 0.3 &mgr;m below the surface of the substrate, and the counterdoped N++ and P++ regions are formed to a depth from about 0.1 &mgr;m to about 0.2 &mgr;m below the surface of the substrate.
Preferably, the deep lightly doped N− and P− regions are formed to a depth from about 0.2 &mgr;m to about 0.3 &mgr;m below the surface of the substrate, with a concentration of phosphorus, p
31
, dopant in the N− regions from about 1 E 17 atoms/cm
3
to about 1 E 18 atoms/cm
3
.
There is a concentration of boron, B, dopant in the P− regions from about 1 E 17 atoms/cm
3
to about 1 E 18 atoms/cm
3
The counterdoped N++ and P++ regions are formed to a depth from about 0.1 &mgr;m to about 0.2 &mgr;m below the surface of the substrate.
There is a concentration of phosphorus, p
31
, or arsenic, As, dopant in the N++ regions from about 5 E 20 atoms/cm
3
to about 1 E 21 atoms/cm
3
and a concentration of boron, B, dopant in the P++ regions from about 5 E 20 atoms/cm
3
to about 1 E 21 atoms/cm
3
.
The S/D regions are formed with a concentration of arsenic, As, dopant in the N+ regions from about 1 E 20 atoms/cm
3
to about 5 E 20 atoms/cm
3
and a concentration of boron, B, dopant in the P+ regions from about 1 E 20 atoms/cm
3
to about 5 E 20 atoms/cm
3
.
The lightly doped S/D regions are formed with a concentration of phosphorus, p
31
, or arsenic, As, dopant in the N− regions from about 1 E 18 atoms/cm
3
to about 1 E 20 atoms/cm
3
and a concentration of boron, B, dopant in the P− regions from about 1 E 18 atoms/cm
3
to about 1 E 20 atoms/cm
3
.


REFERENCES:
patent: 4851257 (1989-07-01), Young et al.
patent: 5130760 (1992-07-01), Matzen et al.
patent: 5493142 (1996-02-01), Randazzo et al.
patent: 5514611 (1996-05-01), Kim et al.
patent: 5559352 (1996-09-01), Hsu et al.
patent: 5663082 (1997-09-01), Lee
patent: 5677224 (1997-10-01), Kadosh et al.
patent: 5686324 (1997-11-01), Wang et al.
patent: 5933721 (1999-08-01), Hause et al.
patent: 5952701 (1999-09-01), Bulucea et al.

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