Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-18
2008-12-16
Nhu, David (Department: 2895)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S649000, C438S682000, C257SE21170, C257SE21324, C257SE21421, C257SE21435, C257SE21438
Reexamination Certificate
active
07465634
ABSTRACT:
An n-FET and a p-FET each have elevated source/drain structures. Optionally, the p-FET elevated-SOURCE/DRAIN structure is epitaxially grown from a p-FET recess formed in the substrate. Optionally, the n-FET elevated-SOURCE/DRAIN structure is epitaxially grown from an n-FET recess formed in the substrate. The n-FET and p-FET elevated-source/drain structures are both silicided, even though the structures may have different materials and/or different structure heights. At least a thermal treatment portion of the source/drain structure siliciding is performed simultaneously for the n-FET and p-FET elevated source/drain structures. Also, the p-FET gate electrode, the n-FET gate electrode, or both, may optionally be silicided simultaneously (same metal and/or same thermal treatment step) with the n-FET and p-FET elevated-source/drain structures, respectively; even though the gate electrodes may have different materials, different silicide metal, and/or different electrode heights. The silicides formed on n-FET and p-FET elevated-source/drain structures preferably do not extend below a top surface of the substrate more than about 250 angstroms; and the structure heights may be selected to provide this.
REFERENCES:
patent: 6413829 (2002-07-01), Yu
patent: 6878592 (2005-04-01), Besser et al.
patent: 7175709 (2007-02-01), Tsai et al.
patent: 7355214 (2008-04-01), Noguchi et al.
Ang, K. H., et al., “Enhanced Performance in 50nm N-MOSFETs with Silicon-Carbon Source/Drain Regions,” 2004 IEEE, IEDM, pp. 1069-1071.
Hou Yong-Tian
Lim Peng-Soon
Tao Hun-Jan
Ying Jin
Nhu David
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Method of forming integrated circuit devices having n-MOSFET... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming integrated circuit devices having n-MOSFET..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming integrated circuit devices having n-MOSFET... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4044734