Method of forming DRAM capacitors with protected outside...

Details Method of forming DRAM capacitors with protected outside... Method of forming DRAM capacitors with protected outside...

2005-04-05

2005-04-05

Pham, Hoai (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S396000

Reexamination Certificate

active

06875655

ABSTRACT:
A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

REFERENCES:
patent: 6130128 (2000-10-01), Lin
patent: 6180483 (2001-01-01), Linliu
patent: 6187624 (2001-02-01), Huang
patent: 6187625 (2001-02-01), Lin et al.
patent: 6730956 (2004-05-01), Bae et al.

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