Method of forming capacitors having high dielectric constant mat

Details Method of forming capacitors having high dielectric constant mat Method of forming capacitors having high dielectric constant mat

1998-12-07

2000-12-19

Elms, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438240, 437 60, 3613214, H01L 218234

Patent

active

061626716

ABSTRACT:
Disclosed is a method of forming storage cell capacitors for use in dynamic random access memories, which comprises, after sequentially depositing a reaction barrier layer and a platinum layer on top of a contact plug which formed on a semiconductor substrate having a node, wet etching the reaction barrier layer to form lateral recesses underneath edges of the platinum layer, and forming sidewall spacer in the lateral recesses and underneath the platinum layer. Also, according to an another embodiment of the invention, a method comprise two important features, one is to surround sidewalls of a reaction barrier layer with an oxide layer, and the other is to form a platinum layer, serving as a storage node electrode of a capacitor, having an inclined plane of more than 80 degrees. The upper portion of the platinum layer has a steeply-sloped pattern of more than 80.degree. inclination angle by two continuous etching steps, one is a dry etch for partially etching the upper portion of the platinum layer and the other is a wet etch for etching the rest of the upper portion thereof.

REFERENCES:
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5559666 (1996-09-01), Figura et al.
patent: 5808854 (1998-09-01), Figura et al.
patent: 6017789 (2000-01-01), Sandhu et al.

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