Method of forming a novel gate electrode structure comprised...

Details Method of forming a novel gate electrode structure comprised... Method of forming a novel gate electrode structure comprised...

2003-01-08

2004-08-24

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S658000, C438S660000

Reexamination Certificate

active

06780741

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a gate structure for a metal oxide semiconductor field effect transistor (MOSFET) device.
(2) Description of Prior Art
Micro-miniaturization, or the ability to form semiconductor devices with sub-micron features, has allowed the performance of sub-micron MOSFET devices to be increased, while processing costs have decreased. However as dimensions of specific device features decrease specific phenomena, not relevant for devices formed with larger features, become significant. For example gate structures, comprised of polysilicon, can exhibit a polysilicon depletion effect (PED), specifically evident with narrow width polysilicon gate structures. The polysilicon depletion effect entails distribution of the applied voltage across the polysilicon gate structure as well as across the intended region, the underlying gate insulator layer. The PED phenomena thus adversely influences critical device characteristics such as threshold voltage. In addition to the PED phenomena encountered with devices fabricated with sub-micron features, the effect of the surface characteristics of the polysilicon gate structure interfacing the underlying gate insulator layer can also magnified. For example a polysilicon layer deposited on an underlying silicon dioxide gate insulator layer is formed with columnar grains, grains that extend vertically from the silicon dioxide-polysilicon interface throughout the polysilicon layer. This type of grain structure or surface roughness, results in unwanted vertical electric scattering, deleteriously influencing specific device parameters such as carrier mobility. The effect of the columnar grains or surface roughness is more pronounced for devices comprised with sub-micron gate structures.
This invention will describe a process sequence used to form a gate structure in which the polysilicon depletion effect is reduced, in addition to reducing polysilicon surface roughness by altering a columnar grain structure to a smoother randomly grained polysilicon layer. This is accomplished via use of a composite gate structure comprised of a polysilicon-germanium layer, used to reduce PED, sandwiched between layers of polysilicon comprised with random grain structures, which in turn are obtained via the novel procedures described in the present invention. Prior art such as Long et al, in U.S. Pat. No. 6,153,534, Yu, in U.S. Pat. No. 6,214,681 B1, Yu, in U.S. Pat. No. 6,180,499 B1, Sagnes, in U.S. Pat. No. 5,998,289, and Anjum, in U.S. Pat. No. 5,633,177, describe methods of forming gate structures, some comprised with silicon-germanium components, however none describing the novel procedures described in the present invention in which a gate structure is formed comprised of a polysilicon-germanium component, located between random grain polysilicon layers, thus providing reduction in a polysilicon depletion effect, as well as providing enhancement of specific device characteristics.
SUMMARY OF THE INVENTION
It is an object of this invention to form a conductive gate structure for a MOSFET device, comprised of a polysilicon-germanium component, sandwiched between two polysilicon layers.
It is another object of this invention to form the two polysilicon layers with smooth surfaces and comprised with random grains.
It is still another object of this invention to perform a low temperature, hydrogen, in situ anneal after deposition of the polysilicon layers to convert the columnar grains of the polysilicon to smaller, random grains.
In accordance with this invention a method of forming a conductive gate structure for a MOSFET device, comprised of a polysilicon-germanium component located between polysilicon layers, which in turn are comprised with small, random grains, is described. After growth of a silicon dioxide gate insulator layer, a polysilicon seed layer, comprised with columnar grains is deposited. A low temperature, in situ anneal procedure performed in a hydrogen ambient, is then employed to convert the columnar grain polysilicon seed layer to a polysilicon seed layer comprised of smaller, random grains, with the smaller random grain polysilicon layer also presenting smoother surfaces than the columnar grain polysilicon counterpart. Deposition of a polysilicon-germanium layer is next accomplished on the smooth top surface of the random grain polysilicon seed layer. This is followed by deposition of a polysilicon cap layer, again comprised of a columnar grain polysilicon layer, which after subjection to another low temperature, in situ hydrogen anneal procedure, evolves into a small, random grain polysilicon layer, exhibiting smooth surfaces. Photolithographic and dry etching procedures are then employed to define a conductive gate structure comprised of a polysilicon-germanium component sandwiched between two polysilicon layers each comprised with small random grains.


REFERENCES:
patent: 5441904 (1995-08-01), Kim et al.
patent: 5633177 (1997-05-01), Anjum
patent: 5817547 (1998-10-01), Eom
patent: 5998289 (1999-12-01), Sagnes
patent: 6153534 (2000-11-01), Long et al.
patent: 6159810 (2000-12-01), Yang
patent: 6180499 (2001-01-01), Yu
patent: 6214681 (2001-04-01), Yu
patent: 6373112 (2002-04-01), Murthy et al.

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