Method of forming a locally strained transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21435

Reexamination Certificate

active

11119522

ABSTRACT:
A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.

REFERENCES:
patent: 6573172 (2003-06-01), En et al.
patent: 6703282 (2004-03-01), Yang et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6902971 (2005-06-01), Grudowski
patent: 2004/0104405 (2004-06-01), Huang et al.
patent: 2004/0113217 (2004-06-01), Chidambarrao et al.
patent: 2004/0200417 (2004-10-01), Hanawa et al.
patent: 2004/0212035 (2004-10-01), Yeo et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0020022 (2005-01-01), Grudowski
patent: 2006/0099765 (2006-05-01), Yang
GE, C.-H., et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” IEEE (2003) 4 pages.
Ghani, T., et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” IEDM (2003) pp. 978-980.
Ito, S., et al., “Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design,” IEDM (2000) pp. 247-250.
Nowling, G.R., et al., “Remote Plasma-Enhanced Chemical Vapour Deposition of Silicon Nitride at Atmospheric Pressure,” Plasma Sources Sci. Technol., vol. 11 (2002) pp. 97-103.
Ootsuka, F., et al., “A Highly Dense, High-Performance 130nm Node CMOS Technology for Large Scale System-on-a-Chip Applications.” IEDM (2000) pp. 575-578.
Scott, G., et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” IEDM (1999) pp. 827-830.
Shimizu, A., et al., “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement,” IEDM (2001) pp. 433-436.
Xiang, Y., et al., “Measuring the Elastic Modulus and Ultimate Strength of Low-K Dielectric Materials by Means of the Bulge Test,” IEEE (2004) pp. 133-135.
Zhang, X., et al., “Residual Stress Characterization of Thick PECVD TEOS Film for Power MEMs Applications,” Solid-State Sensor and Actuator Workshop, (Jun. 2000) pp. 1-4.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of forming a locally strained transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming a locally strained transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a locally strained transistor will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3839101

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.