Method of forming a gate of a non-volatile memory device

Details Method of forming a gate of a non-volatile memory device Method of forming a gate of a non-volatile memory device

2006-03-07

2006-03-07

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S663000, C438S198000

Reexamination Certificate

active

07008844

ABSTRACT:
A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.

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English language of abstract for Korean Patent Publication No. 2000-42639.

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