Method of forming a cup capacitor

Details Method of forming a cup capacitor Method of forming a cup capacitor

2001-06-06

2004-05-04

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06730561

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of forming a capacitor, in particular, a cup capacitor.
2. Brief Description of the Background Art
The implementation of digital information storage and retrieval is a common application of modern digital electronics. Memory size and access time serve as a measure of progress in computer technology. Quite often, storage capacitors are employed as memory array elements. As the state of the art has advanced, high density dynamic random access memory (DRAM) devices require smaller storage capacitors of the same capacitance by, for example, employing high dielectric constant materials or ferroelectric materials. The high dielectric constant materials or ferroelectric materials frequently include sintered metal oxide and may contain a substantial amount of reactive oxygen. In the formation of capacitors employing ferroelectric materials or films, the electrodes must be composed of materials which are difficult to oxidize, to prevent oxidation of the electrodes, which would decrease the capacitance of storage capacitors. Therefore, metals such as platinum, iridium, and ruthenium are preferred metals for use in the manufacture of capacitors for high density DRAMs. These metals are likely to be the preferred electrode materials in future generation memory devices. Platinum has emerged as a particularly attractive candidate because it is inert to oxidation and is known to have a leakage current (<10
−9
amps/cm
2
) which is lower than that of many other metals. Platinum is also a good conductor.
As the state of the art has advanced, various designs for capacitor structures have emerged. One type of design is the cup capacitor, which is also known as a container capacitor or inlaid capacitor. Various cup capacitor designs and manufacturing techniques are described in the art. One method for forming conductive container structures on a supporting substrate of a semiconductor device includes the following steps: forming an insulating layer over parallel conductive lines and existing material on the surface of the supporting substrate; providing openings into the insulating layer, the openings forming vertical sidewalls in the insulating layer that resides between two neighboring conductive lines and thereby exposing an underlying conductive material; forming a sacrificial layer that makes contact with the underlying conductive material; forming a barrier layer overlying and conforming to the sacrificial layer; forming insulating spacers on the vertical sidewalls of the barrier layer; removing portions of the barrier layer and the sacrificial layer that span between the insulating spacers to thereby expose a portion of the underlying conductive material; removing the insulating spacers and thereby exposing the barrier layer; forming a conductive layer that conforms to the exposed barrier layer, makes contact to the underlying conductive material and forms multiple containers; forming a filler material in the container; removing portions of the conductive layer, the barrier layer and the sacrificial layer down to an upper portion of the insulating layer, thereby forming individual container structures; removing the insulating layer, thereby exposing the sacrificial layer surrounding the outer surfaces of the container structures; and removing the sacrificial layer, the remaining barrier layer and the fill layer, thereby exposing the outer and inner surfaces of the container structures.
According to another method for forming a stacked container capacitor, a first dielectric layer, a second dielectric layer, and a patterned mask layer are formed successively upon a semiconductor substrate. An anisotropic etch process is then performed to etch an aperture at least partially through the first dielectric layer using an anisotropic etch process. The second dielectric layer is then selectively etched relative to the first dielectric layer using an isotropic etch process, forming a ledge above the first dielectric layer and below the patterned masking layer. After removal of the masking layer, a first polysilicon layer, a third dielectric layer, and a second polysilicon layer are formed in the etched aperture. The filled aperture is then planarized until a flange of the first polysilicon layer formed into the ledge is exposed.
In a method of forming a container capacitor having a recessed conductive layer, which is typically made of polysilicon, chemical mechanical planarization is used to remove the layer of polysilicon and an overlying layer of photoresist from an upper surface of a substrate in which a container is formed. A wet etch is performed to selectively isolate a rim of the polysilicon within the container to recess the rim, while the remainder of the polysilicon in the container is protected by a photoresist layer.
In another method for forming a high-density DRAM cell with a polysilicon, cup-shaped capacitor, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed on the first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are then removed to define an opening. A second conductive layer is formed conformably on the substrate within the opening and on the first conductive layer. A sidewall structure is then formed within the opening on the sidewalls of the second conductive layer. Next, a portion of the second conductive layer which is not covered by the sidewall structure is removed. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer. A third conductive layer is formed conformably on the substrate to fill up the contact hole. Portions of the first conductive layer and the third conductive layer are removed to define a storage node. The second dielectric layer is then removed and a third dielectric layer is formed on the substrate. Finally, a fourth conductive layer is formed on the third dielectric layer to complete the formation of the capacitor.
A more detailed description of the Background Art described above can be found in U.S. Pat. No. 5,354,705, issued Oct. 11, 1994, to Mathews et al.; U.S. Pat. No. 5,627,094, issued May 6, 1997, to Chan et al.; U.S. Pat. No. 5,963,814, issued Oct. 5, 1999, to Walker et al.; and U.S. Pat. No. 6,090,663, issued Jul. 18, 2000, to Wu.
One prior art process for forming a cup capacitor is illustrated in
FIGS. 3A through 3G
. Referring to
FIG. 3A
, a starting structure
300
for forming a cup capacitor includes, from bottom to top, a semiconductor substrate
301
, a dielectric layer
302
overlying the semiconductor substrate
301
, and a patterned layer
304
of photoresist overlying the dielectric layer
302
. Source
303
and drain
305
regions have been previously formed in semiconductor substrate
301
by ion implantation. Source
303
and drain
305
regions are connected by gate region
307
. A polysilicon plug
306
and diffusion barrier layer
308
have been previously formed in dielectric layer
302
, using conventional techniques known in the art. Polysilicon plug
306
contacts source region
303
. Drain region
305
and gate region
307
are further connected to various interconnects (not shown).
Referring to
FIG. 3B
, dielectric layer
302
is pattern etched, using patterned photoresist layer
304
as a mask and etching techniques known in the art, to form a cup
310
in dielectric layer
302
. Prior to performing further processing steps, the remaining photoresist layer
304
is removed, as shown in FIG.
3
C.
Referring to
FIG. 3D
, a conformal conductive material layer
312
is then deposited over the sidewalls and bottom of the cup
310
, using deposition techniques known in the art to provide a substantially conformal deposition. A layer
314
of a sacrificial material (typically silicon oxide) is then deposited t

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