Method of forming a CMOS type semiconductor device

Details Method of forming a CMOS type semiconductor device Method of forming a CMOS type semiconductor device

2001-12-14

2003-08-26

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S203000, C438S199000

Reexamination Certificate

active

06610565

ABSTRACT:

RELATED APPLICATION
This application relies for priority upon Korean Patent Application No. 2001-24331, filed on May 4, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of forming a CMOS type semiconductor device, and more particularly to a method of forming a CMOS type semiconductor device using disposable spacers.
BACKGROUND OF THE INVENTION
A semiconductor device using MOS transistors generally has contacts for supplying voltage to source/drain regions of transistors. Also, as the elements incorporated in the device are increasingly integrated to a high degree, insulation spacers having an etch selectivity with respect to an interlayer insulation layer are formed on side walls of gate electrodes to prevent a short circuit between the gate electrodes and the contacts formed in the source/drain regions and to form a lightly doped drain (LDD) or dual doped structure easily in the source/drain regions.
However, as the integration degree of the semiconductor device continues to be increased, the sizes of source/drain regions themselves are decreased. Particularly, the area of the source/drain regions is narrowed by the spacers formed on the side walls of the gate electrodes. Also, when an etch stop layer is formed on the gate electrodes on which the spacers are formed, the area of source/drain regions is further narrowed. Therefore, when the source/drain regions between the gate electrodes are filled with an interlayer insulation layer, voids can be formed therein. Also, the contact area between contact plugs and the source/drain regions is reduced to increase the contact resistance. Further, if the spacers are misaligned, the portion of the source/drain regions in which the contacts are to be formed may be blocked and not exposed by the spacers during the etching for forming contact holes. Accordingly, in recent years, a MOS transistor structure which does not have spacers has been proposed and used.
Also, as the integration degree of the semiconductor device is increased, shallow conjunctions are formed in the source/drain regions. To prevent a hot carrier effect or a short channel effect due to the shallow conjunctions, it is required that the dual doped structure be formed in the source/drain regions. As a method for forming the dual doped structure without the spacers, a disposable oxide spacer scheme of removing spacers after forming the dual doped structure in the source/drain regions by using the spacers can be considered.
FIG. 1
to
FIG. 6
are cross-sectional views for illustrating the process steps of a conventional method of forming a CMOS type semiconductor device using disposable spacers. Referring to
FIG. 1
, gate electrodes
110
are formed through a patterning process on a surface of a substrate
100
in which an isolation layer and various wells are formed. An annealing process for curing etch damage is then carried out. Consequently, a thin oxide layer
120
is formed on the surfaces of the substrate
100
and the gate electrodes
110
.
Referring to
FIG. 2
, a silicon nitride layer as an etch stop layer
130
is formed. To form spacers
140
,
150
, a silicon oxide layer is deposited over the whole surface of the substrate
100
on which the etch stop layer
130
is formed. The silicon oxide layer is anisotropically etched to form the spacers
140
,
150
on side walls of the gate electrodes
110
.
Referring to
FIG. 3
, a first photo-resist pattern
160
exposing a NMOS region is formed on the gate electrodes
110
on which the spacers
140
,
150
are formed. The surface of the substrate
100
in the NMOS region is then heavily implanted by an n-type impurity.
Referring to FIG.
3
and
FIG. 4
, the spacers
140
formed on the side walls of the gate electrodes
110
in the NMOS region are removed through a wet etching process which uses the photo-resist pattern
160
exposing the NMOS region as an etch mask. The surface of the substrate in source/drain regions of the NMOS region is then lightly implanted by the n-type impurity. Consequently, a NMOS transistor having a dual doped structure is formed. The dual doped structure has a lightly doped impurity region
164
formed in vicinity of the side walls of the gate electrodes
110
and a heavily doped impurity region
162
formed in the surface of the substrate which is spaced apart as much as a thickness of the spacers
140
from the side walls of the gate electrodes
110
.
Referring to FIG.
4
and
FIG. 5
, the first photo-resist pattern
160
exposing the NMOS region is removed and a second photo-resist pattern
170
exposing the PMOS region is formed. The surface of the substrate
100
in the PMOS region is then heavily implanted by a p-type impurity. The second photo-resist pattern
170
and the gate electrodes
110
of the PMOS region on which the spacers
150
are formed acts as an impurity implantation mask.
Referring to FIG.
5
and
FIG. 6
, the spacers
150
formed on the side walls of the gate electrodes
110
are removed through the wet etching process which uses the second photo-resist pattern
170
as an etch mask. The surface of the substrate
100
in source/drain regions of the PMOS region is then lightly implanted by the p-type impurity. Consequently, a PMOS transistor having a dual doped structure is formed. The dual doped structure has a lightly doped impurity region
174
formed in vicinity of the side walls of the gate electrodes
110
and a heavily doped impurity region
172
formed in the surface of the substrate
100
which is spaced apart as much as a thickness of the spacers
150
from the side walls of the gate electrodes
110
. Thus, a CMOS transistor structure is obtained.
Next, a silicon oxide layer as an interlayer insulation layer is formed over the surface of the substrate on which the CMOS transistor structure is formed. The interlayer insulation layer is etched to form contact holes in source/drain regions. The etch stop layer enclosing the gate electrodes to protect it prevents a short circuit between the gate electrodes and contacts from being formed.
However, in the process described above, when the spacers formed on the side walls of the gate electrodes in the NMOS region are removed through the wet etching as shown in
FIG. 4
, the spacers formed on the side walls of the gate electrodes in the PMOS region on the border of the NMOS region are also partially removed. Accordingly, when the surface of the substrate in the PMOS region is heavily implanted by the p-type impurity, there is no means which can act as the impurity implantation mask on the spacer-removed portion of the gate electrodes in the PMOS region adjacent to the border of the NMOS region. Therefore, in the surface of the substrate
100
in vicinity of the spacer-removed portion of the gate electrodes, the dual doped structure is not formed, but the heavily doped impurity region is formed. Consequently, in the portion of the PMOS transistor without the dual doped structure, a drop in threshold voltage Vt and a change in saturated drain current Idsat due to the short channel effect occur, resulting in the effect that transistor characteristics are degraded.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an improved method of forming a CMOS type semiconductor device using disposable spacers, which can precisely form a dual doped structure in interfaces between channel regions and source/drain regions in the CMOS type semiconductor device.
It is another object of the present invention to provide an improved method of forming a CMOS type semiconductor device which can restrain the hot carrier effect or the short channel effect to prevent degradation in transistor characteristics from occurring.
It is another object of the present invention to provide an improved method of forming a CMOS type semiconductor device which can precisely form a dual doped structure in source/drain regions while providing an area for contacts therein.
These and other objects are provided, acc

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