Method of fabricating metal oxide semiconductor transistor...

Details Method of fabricating metal oxide semiconductor transistor... Method of fabricating metal oxide semiconductor transistor...

2001-11-02

2003-04-01

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S514000

Reexamination Certificate

active

06541328

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a metal oxide semiconductor (MOS) transistor having a lightly doped drain (LDD) structure without a gate spacer.
2. Description of the Related Art
As semiconductor devices have rapidly decreased in size, many changes to the structure of transistors have been required. For example, a short channeled device is required in order to increase the operation speed and in order to produce highly integrated semiconductor devices. As the channel length of the transistors becomes shorter, a problem referred to as the “punch through” phenomenon occurs. In order to address this issue, a shallow junction, which is capable of reducing the strength of an electric field between a source region and a drain region during the operation of a transistor, is realized.
Processes of forming a lightly doped drain (LDD) structure, which have been used in forming such a shallow junction, will now be described. First, a gate electrode is formed on a semiconductor substrate. Low density impurity ions are implanted into a source/drain region using a gate electrode as a mask, and then annealing is performed. Spacers are formed on both side walls of the gate electrode. High density impurity ions are implanted into the source/drain region using the gate electrode and the spacers as masks, and then annealing is performed.
In the above-mentioned conventional method of fabricating the transistor with the LDD structure, a low density source/drain region is formed before forming a high density source/drain region. Therefore, thermal stress of the low density source/drain region increases and diffusion of impurities may occur since the low density source/drain region undergoes an annealing process twice. Also, in forming a metal silicide film in an active region or in the gate electrode, the distance between gate spacers becomes narrower as the pattern of a transistor becomes smaller. Therefore, it is not easy to form the metal silicide film.
Processes of forming the LDD structure of a complementary metal oxide semiconductor (CMOS) obtained by combining a p-type MOS (PMOS) with an n-type MOS (NMOS) will now be described. The conductivity type of the channel in the PMOS is different from the conductivity type of the channel in the NMOS. A semiconductor substrate, in which the PMOS is to be formed, is covered with a photoresist pattern. Low density n-type impurity ions are implanted into a substrate in region where the NMOS is to be formed. Then, after removing the photoresist pattern, the semiconductor substrate, in which the NMOS is formed, is covered with another photoresist pattern. Low density p-type impurity ions are implanted into the substrate in a region where the PMOS is to be formed. After removing the photoresist pattern, spacers are formed on the side walls of the gate electrodes of the PMOS and the NMOS. The semiconductor substrate, in which the PMOS is formed, is covered with the photoresist pattern. High density n-type impurity ions are implanted into the substrate where the NMOS is formed. Then, after removing the photoresist pattern, the semiconductor substrate, in which the NMOS is formed, is covered with still another photoresist pattern. High density p-type impurity ions are implanted into the substrate where the PMOS is formed.
It is a complicated, and therefore expensive, procedure to perform a photoresist pattern process four times in order to form transistors having channels of different conductivity type on the semiconductor substrate.
SUMMARY OF THE INVENTION
To address the above limitations, it is a first object of the present invention to provide a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure in which the thermal stress of a low density source/drain region is minimized and in which a metal suicide film can be easily formed.
It is a second object of the present invention to provide a method of fabricating a MOS transistor with a complementary metal oxide semiconductor (CMOS) LDD structure in which the processes of the method are simplified.
Accordingly, to achieve the first object, there is provided a method of fabricating a metal oxide semiconductor (MOS) transistor. Gate electrodes are formed on a semiconductor substrate. Spacers are formed on both side walls of the gate electrodes. First impurity regions having a first density are formed on both sides of the spacers in the semiconductor substrate. The spacers are removed. Second impurity regions having a second density that is lower than the first density are formed on both sides of the gate electrodes in the semiconductor substrate.
It is preferable that between the formation of the gate electrodes and the formation of the spacers, insulating films are formed at both edges formed by the semiconductor substrate and the gate electrodes such that undercuts are formed between the gate electrodes and the spacers and between the spacers and the semiconductor substrate. In the step of forming the insulating films, an insulating material layer is formed on the entire surface of the semiconductor substrate, on which the gate electrodes are formed; spacers having a different etching selectivity from the etching selectivity of the insulating material layer are formed on the side walls of the gate electrodes, on which the insulating material layer is formed; and the insulating material layer is etched such that undercuts are formed between the gate electrodes and the spacers and between the semiconductor substrate and the spacers.
The insulating films are preferably formed to have “L” shaped cross-sections. The insulating films are formed of Si
3
N
4
. A metal silicide film is formed on the semiconductor substrate where the first impurity regions are formed, on the gate electrodes, and on the upper side walls of the gate electrodes, on which the insulating films are not formed. In the step of forming the first impurity regions, first impurities are ion implanted into the semiconductor substrate using the gate electrode and the spacers as masks. The spacers are formed of polysilicon. The spacers are removed using, for example, NH
4
OH.
To achieve the second object, there is provided a method of fabricating a MOS transistor. A first region and a second region are formed on a semiconductor substrate. A first gate electrode and a second gate electrode are formed on the first region and the second region of the semiconductor substrate, respectively. Spacers are formed on both side walls of the first gate electrode and the second gate electrode. The entire surface of the semiconductor substrate in the second region covered with a first mask. First impurity regions doped with a first conductivity type material having a first density are formed in the semiconductor substrate in the first region. The spacers of the first region are removed. Second impurity regions doped with the first conductivity type material having a second density that is lower than the first density are formed in the semiconductor substrate on both sides of the first gate electrode exposed by removing the spacers of the first region. After removing the first mask, the entire surface of the semiconductor substrate of the first region is covered with a second mask. Third impurity regions doped with a second conductivity type material having a third density are formed in the semiconductor substrate in the second region using the spacers and the second gate electrode formed in the second region as masks. The spacers of the second region are removed. Fourth impurity regions doped with the second conductivity type material having a fourth density that is lower than the third density are formed in the semiconductor substrate on both sides of the second gate electrode exposed by removing the spacers of the second region.
Preferably, between the formation of the first and second gate electrodes and the formation of the spacers, insulating films are

Affiliated with

Also associated with

Rating

Method of fabricating metal oxide semiconductor transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating metal oxide semiconductor transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating metal oxide semiconductor transistor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3044970