Method of depositing low K films

Details Method of depositing low K films Method of depositing low K films

2003-02-25

2004-10-19

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S005000, C438S780000, C438S790000

Reexamination Certificate

active

06806207

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing dielectric layers on a substrate.
BACKGROUND OF THE INVENTION
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526, entitled “Plasma-Enhanced CVD Process Using TEOS for Depositing Silicon Oxide”, which is incorporated by reference herein. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone, thereby creating a plasma of highly reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 &mgr;m and even 0.18 &mgr;m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant<4.0) to reduce the capacitive coupling between adjacent metal lines. Liner/barrier layers have been used between the conductive materials and the insulators to prevent diffusion of byproducts such as moisture onto the conductive material. For example, moisture that can be generated during formation of a low k insulator readily diffuses to the surface of the conductive metal and increases the resistivity of the conductive metal surface. A barrier/liner layer formed from conventional silicon oxide or silicon nitride materials can block the diffusion of the byproducts. However, the barrier/liner layers typically have dielectric constants that are significantly greater than 4.0, and the high dielectric constants result in a combined insulator that does not significantly reduce the dielectric constant.
The deposition of silicon oxide films that contain carbon and have low dielectric constants is described in World Patent Publication No. WO 99/41423, which published on Aug. 19, 1999, and is incorporated by reference herein. Films having dielectric constants of about 3.0 or less are deposited from organosilicon compounds at conditions sufficient to deposit silicon oxide films that contain from 1% to 50% carbon by atomic weight carbon-containing films. Curing of the films to remove moisture improves the barrier properties of the films. The retention of carbon in the films contributes to the low dielectric constants. Carbon is more readily retained in the films at deposition conditions that do not fully remove moisture from the films, thus, favoring deposition and then curing of the film. However, films that retain substantial moisture may shrink and crack during curing which detracts from the smoothness of the film or subsequent layers. Process conditions that avoid shrinkage of the films are desired.
SUMMARY OF THE INVENTION
The present invention provides a method for depositing a silicon oxide layer having low moisture content and a low dielectric constant. The silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. Preferably, the plasma is generated at a power density ranging between 0.9 W/cm
2
and about 3.2 W/cm
2
. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds.
Another aspect of the invention provides for controlling process conditions to deposit a silicon oxide layer having an atomic ratio of carbon to silicon (C:Si) of greater than or equal to about 1:9. Preferably the atomic ratio of carbon to silicon (C:Si) is less than about 1:1. The silicon oxide layer is produced by plasma enhanced decomposition of an organosilicon compound, preferably in the presence of an oxidizing gas and an inert carrier gas.
The silicon oxide layers can replace conventional or low k silicon oxide layers such as in intermetal dielectric layers, as dielectric layers in a damascene process, or as adhesion layers.


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