Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-01-02
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S720000, C438S722000, C438S725000, C438S906000, C134S001000, C134S001100, C134S001200, C134S001300
Reexamination Certificate
active
06319842
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor processing and in particular to cleaning of an inprocess semiconductor wafer to remove contaminants that could impair the operation of the semiconductor device.
BACKGROUND OF THE INVENTION
The fabrication of an integrated circuit chip normally includes the deposition of metal and dielectric layers over the surface of the semiconductor substrate. The metal layers are separated by the dielectric layers and are patterned to form the desired circuit paths in the device. Interconnections between the metal layers are formed by creating vertical openings, or “vias”, which are then filled with metal, through the dielectric layers.
Patterning of the dielectric and metal layers can be accomplished using photoresist. A layer of photoresist is deposited on the underlying layer, and the photoresist is exposed to light in the desired pattern and developed to form a mask which is used to transfer the pattern to an underlying metal or dielectric layer. The transfer process generally involves a reactive plasma treatment in which reactive gas species and directional ion bombardment are used to etch the desired pattern into the metal or dielectric.
These processes typically leave residues of various materials, for example, photoresist, which must be removed to preserve the integrity of the finished device. In addition, the metal layers can become oxidized, and the resulting oxide layers must be removed to assure good ohmic contacts between the different metal layers. The contaminants must be removed, in particular from the vias, and, generally speaking, the contaminants are more difficult to remove as the aspect ratio of the via (i.e., the ratio of its depth to its width) increases. On the other hand, the removal of these contaminants should be carried out in a way that does not significantly alter the structure of the alternating metal and dielectric layers.
One cleaning process is suggested in U.S. Pat. No. 5,660,682 to Zhao et al. The process is described as follows:
The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the integrated circuit is kept within the plasma, thereby converting the material to gaseous byproducts, for a length of time sufficient to remove at least some of the material from the integrated circuit. (Col. 2, lines 31-39)
The plasma ionizes the argon and hydrogen atoms and reates active excited H*, H
2
* species. The argon ions physically bombard contaminants such as polymers and oxides, dislodging them, but in vias with high aspect ratios the polymers and oxides may redeposit of the walls of the vias. For this reason, the argon ions are “supplemented” with the hydrogen ions and active H* species. The reaction between the hydrogen ions, the H* species and the polymers produces water vapor and hydrocarbon gas, and the reaction between the hydrogen ions, the H* species and the oxide produces gaseous SiH
x
. These gases do not redeposit on the sidewalls of the vias and can be removed from the chamber by pumping. (Col. 3, line 65, to col. 4, line 6) The physical and chemical processes take place simultaneously.
There are several possible problems with the process taught in the Zhao et al. patent. First, the physical action of the argon ions not only removes contaminants but also tends to create faceting at the upper comers of the vias, as shown in FIG.
1
. This may limit the minimum separation between lines. Second, where the via is formed over a copper layer, the physical action of the argon ions may cause a significant amount of copper, copper oxide and other contaminants to be sputter deposited on the sidewalls of the vias. The copper may then diffuse into the dielectric layer and become mobile under the influence of electric fields or may diffuse during thermal processing. This can cause line-to-line leakage currents to flow through dielectric layer during the operation of the device. Third, contamination on the sidewalls of the vias may adversely affect the wetting properties of the dielectric, causing problems in later processing. In particular, barrier and seed layers deposited on the dielectric may not adhere properly, and voids may be formed when the via is filled with metal by a process such as electrochemical deposition. Such voids increase the resistance of the metal “posts” extending through the vias and connecting the overlying and underlying metal layers and raise concerns about device reliability.
Accordingly, there is a need for a process for cleaning a semiconductor structure which avoids the possible problems of the technique described in the Zhao et al. patent.
SUMMARY OF THE INVENTION
In accordance with this invention, a semiconductor structure is cleaned in multi-stage (i.e., at least a two-stage) process. In a first stage, a plasma is formed adjacent to the structure, the plasma including an inert gas. Power is applied to the plasma at a higher level, the higher level being set such that ions of the inert gas collide with the semiconductor structure and thereby cause atoms of a contaminant to be dislodged from the structure. A reducing gas is introduced to the inert gas plasma. In the following stage, the power applied to the plasma is decreased to a lower level such that the ions of the inert gas generally do not have sufficient energy to cause atoms of the contaminant to be dislodged from the structure; and the reducing gas is allowed to react with the metallic oxide in the semiconductor structure. The power can be decreased from the higher level to the lower level gradually or in one or more steps, or in a combination of ramps and steps.
In some embodiments the inert gas comprises argon and the reducing gas comprises hydrogen. The contaminant may include a hydrocarbon a fluorocarbon, or both.
The process can be used with a variety of metals but is particularly useful when the structure comprises a copper conductor, in which case the reducing gas reacts with the oxides of copper to form pure copper. The process is also particularly suited to structures which contain a via in the dielectric layer.
Decreasing the power from the higher level to the lower level essentially terminates the physical sputtering process when the nonvolatile contaminants (e.g., hydrocarbons and fluorocarbons) have been removed and before the sputtering has created facets on the upper comers of the via. Also, the physical sputtering is terminated before appreciable amounts of copper have been deposited on the sidewalls of the via.
Thus the multi-stage process of this invention avoids many of the problems of the prior art, including the Zhao et al. patent.
REFERENCES:
patent: 4357203 (1982-11-01), Zelez
patent: 5432073 (1995-07-01), Wu et al.
patent: 5660682 (1997-08-01), Zhao et al.
Allen Ronald D.
Khosla Mukul
Klawuhn Erich
Powell Ronald A.
Rozbicki Robert T.
Niebling John F.
Novellus Systems Incorporated
Skjerven Morrill & MacPherson LLP
Steuber David E.
Zarneke David A
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