Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-10-05
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S787000, C438S789000, C427S099300, C427S515000, C427S578000
Reexamination Certificate
active
06258735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing a carbon doped silicon oxide layer on a substrate.
2. Background of the Related Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone, thereby creating a plasma of highly reactive species.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 &mgr;m and even 0.18 &mgr;m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having a low k (dielectric constant <4.0) to reduce the capacitive coupling between adjacent metal lines. An example of films having dielectric constants of about 3.0 or less are films deposited from organosilicon compounds, such as organo silanes and organo siloxanes, at conditions sufficient to deposit silicon oxide films containing from about 1% to about 50% carbon by atomic weight.
However, typical deposition processes may result in wafer damage reducing yield and increasing production costs. One such deposition technique simultaneously introduces an oxidizer and an organosilicon compound into a deposition chamber prior to striking plasma. The ignition of the oxidizer and organosilicon mixture causes a pressure spike due to the disassociation of the organosilicon compound into fragments that increases gas density. The initial increase in ionization induces charge on the wafer and can cause wafer damage. Additionally, wafer damage caused by arcing can occur when electro current strikes through the deposited films due to a high current causing excessive heating and resulting in spotting, i.e., a circular, ring like burn mark, on the wafer surface.
Another typical deposition technique involves igniting a first plasma in a first environment to deposit an oxide layer, terminating the first plasma, then igniting a second plasma in a second environment to deposit a carbon doped silicon oxide layer on a substrate. The termination step between the two plasma steps, i.e., stopping and starting plasma at different process conditions, induces charge on the wafer by allowing the build up of ionic contaminants and particulates causing wafer damage. One approach to prevent wafer damage caused by arcing and spotting is to deposit a thicker thermal oxide layer, however, the increased thickness results in a higher k film.
One indicator of wafer damage caused by, for example, ionic contaminants, arcing, spotting and tunneling, i.e., ionic striking, or induced current, across the wafer due to an uneven charge distribution which can result in shorting, is the plasma damage measurement (PDM). The PDM is typically calculated by measuring the voltage across the surface of the wafer at a number of points and then subtracting the minimum from the maximum. Generally, the larger the voltage difference across the wafer the greater the wafer damage.
Therefore, process conditions for depositing carbon doped silicon oxide films are desired.
SUMMARY OF THE INVENTION
The present invention generally relates to a process of depositing a carbon doped silicon oxide film having a low dielectric constant (k) on a substrate. In one aspect, the concentration of oxygen is controlled to produce soft plasma conditions inside the chamber while a precursor gas is diverted through a bypass line to stabilize precursor gas flow prior to routing the precursor gas into the chamber.
In another aspect, a method is provided in which a substrate is positioned in a processing chamber and an oxidizer is introduced into the processing region and a plasma is ignited. A carbon silicon gas source is flowed through a bypass line to stabilize the gas flow. Then, the precursor gas is introduced into the chamber and a back to back plasma is maintained to deposit a carbon doped silicon oxide film on the substrate.
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Lim Tian-Hoe
Nguyen Huong Thanh
Sugiarto Dian
Xia Li-Qun
Applied Materials Inc.
Ghyka Alexander G.
Niebling John F.
Thomason Moser & Patterson
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