Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-08
1998-10-27
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438381, 438382, 438597, H01L 518234
Patent
active
058277641
ABSTRACT:
The present invention provides a method of forming a low contact resistance butt contact 44 between a doped region 30 and a conductive line 16B 18B. The method begins by providing an isolation region 11 on a substrate. A conductive structure 16B 18B comprised of a first polysilicon line 16B and a tungsten silicide layer 18B is formed over the isolation region 11. The substrate has a butt contact area 28 adjacent to the isolation region 11. An inter-poly oxide layer 24 is formed over the resulting surface. A butt contact photoresist layer 26 having an opening 26A exposing the butt contact area 28 and adjacent portions of the isolation region 11 is formed over the oxide layer 24. In an important step, the exposed portions of inter-poly oxide layer 24 and the underlying "high resistivity" tungsten silicide line 18B are etched thereby exposing portions of the first polysilicon layer 16B 16C. In a second key step, ions are implanted into the butt contact area 28 and the exposed portions of the first polysilicon layer 16C. The butt contact 44 is completed by depositing a second polysilicon layer 40 over the inter-poly oxide layer 24, over the exposed portion of the first polysilicon layer 16C and over the substrate in the Butt contact area 28.
REFERENCES:
patent: 4410375 (1983-10-01), Sawada et al.
patent: 4877483 (1989-10-01), Bergemont et al.
patent: 4994402 (1991-02-01), Chiu
patent: 5358903 (1994-10-01), Kim
patent: 5686336 (1997-11-01), Lee
Lee Jin-Yuan
Liaw Jhon-Jhy
Ackerman Stephen B.
Chang Joni
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company , Ltd.
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