Method for preventing voids in metal interconnects

Details Method for preventing voids in metal interconnects Method for preventing voids in metal interconnects

2006-10-17

2006-10-17

Thai, Luan (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S663000, C438S795000, C438S508000, C438S508000, C438S675000, C438S672000

Reexamination Certificate

active

07122471

ABSTRACT:
A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

REFERENCES:
patent: 5932289 (1999-08-01), Dobson et al.
patent: 6124205 (2000-09-01), Doan
patent: 6863491 (2005-03-01), Cheng et al.
patent: 2003/0168346 (2003-09-01), Hey et al.

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