Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-18
2003-11-18
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S253000, C438S393000, C438S396000
Reexamination Certificate
active
06649464
ABSTRACT:
This application claims priority from Korean Patent Application No. 2001-47145, filed on Aug. 4, 2001, the contents of which are incorporated herein by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a capacitor and a via contact
2. Description of the Related Art
In recent years, as the integration density of semiconductor devices increases, the area occupied by individual devices continues to decrease. Specifically, a capacitor for storing data of a dynamic random access memory (DRAM) is required to have sufficient capacitance irrespective of the decrease in the area occupied by the capacitor. Accordingly, a metal-insulator-metal (MIM) capacitor, in which a lower electrode and an upper electrode are formed of metal, has been suggested.
In order to form upper and lower electrodes of a metal layer in a MIM capacitor, an etching process for patterning the metal layer is required. However, as the integration density of semiconductor devices increases, it becomes more difficult to etch the metal layer. In particular, copper, which has good electromigration resistance and a low resistivity of about 1.7 Wcm, is very difficult to etch. Accordingly, a method for forming upper and lower electrodes through a damascene process, in which a process for etching a metal layer is not performed, has been proposed. In U.S. Pat. No. 6,025,226, a method for forming a MIM capacitor and a via contact using a damascene process is disclosed. This method will be described with reference to the accompanying drawings.
FIGS. 1 through 7
are cross-sectional views illustrating a conventional method for forming a MIM capacitor and a via contact using the damascene process disclosed in U.S. Pat. No. 6,025,226. As shown in
FIG. 1
, a first interconnection layer
101
, which includes a first conductive interconnection
110
and a second conductive interconnection
115
, is formed on a first interlayer insulating layer
105
. Next, a second interlayer insulating layer
107
is formed on the first and second conductive interconnections
110
and
115
. As shown in FIG.
2
, the second interlayer insulating layer
107
is patterned, thereby forming a first opening
120
and a second opening
130
. The first and second openings
120
and
130
expose the surfaces of the first and second interconnections
110
and
115
, respectively.
As shown in
FIG. 3
, an insulating layer
122
is deposited on the entire surface of the structure including the first and second openings
120
and
130
. Next, as shown in
FIG. 4
, a trench
132
is formed over the second opening
130
. During an etching process for forming the trench
132
, the first opening
120
and the insulating layer
122
in the first opening
120
are protected from the etching process by a predetermined mask layer pattern. On the other hand, during the etching process, the insulating layer
122
formed at the bottom of the second opening is removed. The trench
132
has a width greater than the width of the second opening
130
.
Next, as shown in
FIG. 5
, a first conductive material
124
is deposited in the first and second openings
120
and
130
and is polished until the second interlayer insulating layer
107
is exposed. Next, as shown in
FIG. 6
, a third interlayer insulating layer
109
is formed on the second interlayer insulating layer
107
and the first conductive material
124
and is patterned to form a third opening
140
. The third opening
140
exposes the surface of the first conductive material
124
filling the first and second openings
120
and
130
. Next, as shown in
FIG. 7
, a second conductive material is deposited on the resulting structure including the third opening
140
to fill the third opening
140
.
Because the conventional method for forming a MIM capacitor and a via contact employs a damascene process, there is no need to perform an etching process on a metal layer which can hardly be etched. However, this method has the following problems.
First, the insulating layer
122
is simultaneously formed on a MIM capacitor region and a via contact region. Because the insulating layer
122
acts as a dielectric layer of the MIM capacitor, the insulating layer
122
must be formed in the MIM capacitor region. However, it must not exist in the via contact region. Accordingly, the insulating layer
122
formed at the bottom of the second opening
130
in the via contact region must be removed, as shown in FIG.
4
. Between removing the insulating layer
122
from the bottom of the second opening
130
and forming a barrier metal layer (not shown), a radio frequency (RF) etching process must be performed to remove a native oxide layer. However, the RF etching process may damage the surface of a capacitor dielectric layer. Accordingly, the performance of a MIM capacitor may deteriorate.
Second, because the insulating layer
122
exists on the sidewalls of the first conductive material
124
, the resistance of a via contact decreases, but the aspect ratio of the via contact increases. Accordingly, it becomes difficult to properly deposit the first conductive material.
SUMMARY OF THE INVENTION
A method for manufacturing a semiconductor device having a via contact and a capacitor includes forming first and second portions of a first metal layer in trenches formed in a first interlayer insulating layer. A second interlayer insulating layer is formed to cover the first portion of the first metal layer and has an opening that exposes the second portion of the first metal layer. A dielectric layer is formed on the exposed second portion of the first metal layer. A second metal layer is formed on the dielectric layer to fill the opening in a capacitor region. A via contact hole to expose the first portion of the first metal layer is formed in the second insulating layer. A third metal layer is formed in the via contact hole. A third interlayer insulating layer is formed on the second interlayer insulating layer. Contact holes to expose the second metal layer and the third metal layer are formed in the third interlayer insulating layer. A fourth metal layer is formed in the contact holes.
Preferably, forming the first metal layer includes forming a mask layer pattern that exposes the via contact region and the capacitor region on the first interlayer insulating layer, forming trenches a predetermined distance apart in the via contact region and the capacitor region by etching the first interlayer insulating layer to a predetermined depth using the mask layer pattern as an etching mask, removing the mask layer pattern, forming a metal layer to fill the trenches, and forming the first and second portions of the first metal layer to be isolated from each other by planarizing the resulting structure including the first metal layer to expose the surface of the first interlayer insulating layer. The method may further include forming a first barrier metal layer between the first interlayer insulating layer and the first metal layer.
Preferably, the method may further include forming a first capping layer on the surfaces of the first interlayer insulating layer and the first metal layer after forming the first metal layer. Here, the first capping layer may be formed of nitride to a thickness of 200-1000 Å.
The second interlayer insulating layer and the first capping layer are etched to have an opening therein to expose the surface of the first metal layer in the capacitor region. The second interlayer insulating layer is preferably formed of oxide to a thickness of 3000-10000 Å.
The dielectric layer is preferably an oxide layer, a nitride layer, or a composite layer including an oxide layer and a nitride layer.
Forming the second metal layer preferably includes forming a second metal layer on the dielectric layer and planarizing the resulting structure including the second metal layer to expose the surface of the second interlayer
Jr. Carl Whitehead
Marger & Johnson & McCollom, P.C.
Nguyen Thanh
Samsung Electronics Co,. Ltd.
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