Method for manufacturing high density flash memory and high...

Details Method for manufacturing high density flash memory and high... Method for manufacturing high density flash memory and high...

2007-03-06

2007-03-06

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

10705192

ABSTRACT:
A method of forming high performance logic transistors and high density flash transistors on a single substrate is disclosed. In one embodiment, the method comprises: forming a logic gate stack in a logic region on a substrate, forming a flash memory gate stack in a flash region on the substrate, depositing a hardmask layer over the logic gate stack and over the flash memory gate stack, patterning the hardmask in the logic region so that areas of hardmask remain where logic gates are desired, patterning the flash gate stack in the flash region to form flash memory gates, and etching the logic gate stack using the remaining hardmask as a mask to form logic gates.

REFERENCES:
patent: 6235587 (2001-05-01), Hsaio et al.
patent: 6417086 (2002-07-01), Osari
patent: 2004/0043592 (2004-03-01), Goodwin et al.
patent: 1 156 524 (2001-11-01), None
PCT Search Report, International Application No. PCT/US2004/036096, filing date Oct. 29, 2004, mailed Apr. 21, 2005 (9 pages).

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