Method for manufacturing a metal-insulator-metal capacitor

Details Method for manufacturing a metal-insulator-metal capacitor Method for manufacturing a metal-insulator-metal capacitor

2003-05-05

2004-03-02

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S250000, C438S381000

Reexamination Certificate

active

06699749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a method for manufacturing a metal-insulator-metal (MIM) capacitor; more particularly, a method for manufacturing a MIM capacitor having a bottom electrode including copper, which can effectively prevent the lifting of thin films and the oxidation of the bottom electrode.
2. Discussion of the Related Art
As semiconductor devices become more highly integrated and the usage of the semiconductor devices in electronic devices, such as information processing apparatuses and home appliances, increases, the semiconductor devices are required to have a larger processing capacity and faster processing speed.
In general, the storage capacity of a random access memory (RAM) chip can be expressed empirically by using Moore' law indicating the general development of a memory chip. According to Moore' law, the storage capacity of a memory chip increases four times every three years. The increase of the storage capacity of a memory chip is accomplished by reducing the size of the semiconductor device, and increasing the length of a silicon chip in accordance with the size reduction of the semiconductor device.
As the size of the semiconductor device installed in the silicon chip is reduced, interconnect lines of the semiconductor device are also reduced. The reduction in the size of a semiconductor device also causes the interconnect lines to be disposed closer together. When the interconnection lines are closely disposed, the interconnect lines interfere with each other. If the interval between the interconnection lines falls below a predetermined value, the entire signal is delay because of the interference between the interconnection lines. To increase the processing speed of a semiconductor device, a reduction of the specific resistance in the metal used for forming the interconnection lines is required.
Typically, the interconnection lines of a semiconductor device are formed using aluminum (Al) or aluminum alloy having the specific resistance of approximately 2.66 &mgr;&OHgr; cm. In 1998, International Business Machine Co. disclosed a method for forming interconnection lines with copper (Cu). Various researchers have been developing methods for forming and improving the formation of interconnection lines, e.g., a metal wiring or a metal-insulator-metal (MIM) capacitor using copper.
Other methods of forming a semiconductor device using copper are disclosed in U.S. Pat. No. 5,935,762 (issued to Chang-Ming Dai), Korean Laid Open Patent Publication No. 2001-110919, and Korean Laid Open Patent Publication No. 2002-55887.
In addition, Japanese Laid Open Patent Publication No. 2000-352827 provides a method for removing a hardened photoresist generated during the patterning of an insulation film using a non-oxidation gas after the insulation film is formed on a metal film including copper. Also, Japanese Laid Open Patent Publication No. 2000-82695 discloses a method for removing a copper halide based compound formed during the etching of a copper thin film with a halogen gas like chlorine (Cl
2
) after forming a passivation film including titanium (Ti), titanium compound, tantalum compound, tungsten compound or aluminum alloy on the copper thin film.
FIGS. 1A
to
1
C are cross-sectional views illustrating a conventional method of manufacturing a metal-insulator-metal capacitor including a copper bottom electrode.
Referring to
FIG. 1A
, after an interlayer dielectric film
15
including oxide is formed on a semiconductor substrate
10
such as a silicon wafer, the interlayer dielectric film
15
is etched to form a groove or a trench in the interlayer dielectric film
15
.
With a copper damascene process, a copper film is deposited in the trench or the groove by a sputtering process, a chemical vapor deposition process, or an electro plating process. Then, the copper film is polished using a chemical-mechanical polishing (CMP) process, thereby forming a metal wire
20
in the interlayer dielectric film
15
.
Subsequently, a dielectric film
25
is formed on the interlayer dielectric film
15
including the copper metal wire
20
, and a top electrode film
30
is formed on the dielectric film
25
. The top electrode film
30
includes tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN).
Referring to
FIG. 1B
, to manufacture the MIM capacitor, a photoresist film is coated on the top electrode film
30
, and the photoresist film is patterned so that a photoresist pattern
35
is created for forming a top electrode of the MIM capacitor.
Referring to
FIG. 1C
, the top electrode film
30
is etched using the photoresist pattern
35
as an etching mask such that the top electrode
40
is formed on the dielectric film
25
.
When the photoresist pattern
35
is removed using an ashing process and a rinsing process, the MIM capacitor
50
having the copper bottom electrode is formed on the substrate
10
.
In a conventional method for manufacturing the MIM capacitor, a hard metallic polymer is formed when the top electrode film having a thickness of below 1,000 Å is etched, forming the top electrode. The hard metallic polymer includes metal oxide or metal nitride like tantalum oxide (TaO
x
), tantalum nitride (TaN
x
), titanium oxide (TiO
x
), titanium nitride (TiN
x
) or carbon nitride (CN
x
) wherein x denotes a positive number. It is difficult, if not impossible, to remove the hard metallic polymer by using an ashing process or a wet cleaning process.
FIGS. 2A and 2B
are cross-sectional views showing the disadvantages of the conventional method for manufacturing the MIM capacitor.
Referring to
FIGS. 1B and 2A
, when the top electrode film
30
is etched using the photoresist pattern
35
as the etching mask, the metal or the metal compound of the top electrode film
30
such as tantalum, tantalum nitride, titanium, or titanium nitride can be reacted with an etching gas including chlorine (Cl
2
), nitrogen (N
2
) and boron chloride (BCl
3
). As a result, the hard metallic polymer
55
including metal oxide or metal nitride adheres to the side of the photoresist pattern
35
.
Because the hard metallic polymer
55
cannot be removed using the ashing or the wet cleaning process, the hard metallic polymer
55
remains on the top electrode
40
of the MIM capacitor
50
even after the photoresist pattern
35
is removed. While performing a successive process, the hard metallic polymer
55
remains and a metal wiring is formed on the MIM capacitor
50
and electrically connects the top electrode
40
of the MIM capacitor
50
. Thus, an electrical short is formed between the MIM capacitor
50
and the metal wiring.
The hard metallic polymer
55
can be removed using a high temperature ashing process that uses an O
2
gas and a CF
4
gas at a high temperature, e.g., above 250° C. As shown in
FIG. 2
, the thin films of the MIM capacitor
50
like the bottom electrode, the dielectric film, and the top electrode may be lifted because of the different thermal characteristics, e.g., coefficient of thermal expansion, of each of the thin films influenced by the high temperature associated with the ashing process. In particular, the top electrode and the dielectric film may be lifted during the high temperature ashing process.
In addition, the copper bottom electrode and other metal film may be easily oxidized during the high temperature ashing process, which creates a MIM capacitor having a uniform capacitance or the capacitance of the MIM capacitor may not meet a desired value. Thus, the overall failure rate of the capacitor may be high during the manufacturing process. Those failures may relate to the thermal characteristics of the thin films of the MIM capacitor, and to the structural characteristic of the MIM capacitor including the thin films having a thickness of below 1,000 Å.
A need therefore exists for a method of manufacturing a metal-insulator-metal (MIM) capacitor which prevents oxidizing of a bottom electrode and lifting of thin films of the MIM capacit

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