Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-24
2001-11-20
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S677000, C438S106000, C438S612000, C438S611000
Reexamination Certificate
active
06319828
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention generally relates to a method for manufacturing semiconductor packages, and more particularly, for manufacturing a chip scale package (“CSP”).
2. Description of the Related Art
Electronic industry trends, such as miniaturization and multifunctionalization of electronic devices, have resulted in a relatively new semiconductor package called a Ball Grid Array (“BGA”) package. When compared to conventional plastic packages, the BGA package has a higher surface-mounting density and superior electrical capabilities. In some respects, however, the BGA package is not as reliable as some conventional packages. Unlike a conventional plastic package that uses moisture-resistant lead frames, the BGA package uses a printed circuit board that is more moisture-prone. Another disadvantage of the BGA package is that space must be reserved on the board for mounting the semiconductor chip. In view of the foregoing drawbacks, a Chip Scale Package (“CSP”) has been proposed.
Many companies in the United States, Japan and Korea have developed or manufactured various types of CSPs. One such type of CSP is called the Fine Pitch BGA (“FPBGA”) package. The &mgr;-BGA package, developed by Tessera in the U.S., is an example of a FPBGA package. The FPBGA packages employ a thin and flexible circuit board, such as a tape wiring board. The flexible circuit board includes beam leads that connect to bonding pads of a semiconductor chip through windows formed in the board.
FIG. 1
is a cross-sectional view of a conventional &mgr;-BGA package
200
. Referring to
FIG. 1
, a tape wiring board
120
includes a polyimide tape
124
having top and bottom surfaces. Copper (Cu) traces
130
are formed on the bottom surface of the polyimide tape
124
. Beam leads
160
extend from the Cu traces
130
. An elastomer layer
150
is interposed between the wiring board
120
and a semiconductor chip
110
. Beam leads
160
, bonded to bonding pads
112
on the semiconductor chip
110
, electrically connect bonding pads
112
to respective solder bumps
168
via the Cu traces
130
and the solder ball mounting pads
136
.
The solder ball mounting pads
136
are portions of the Cu traces
130
that are exposed through connection holes
123
. An encapsulant
189
encapsulates the bonding area between the bonding pads
112
and the beam leads
160
to protect the area from external environmental stresses. The beam leads
160
also comprise portions of the Cu traces
138
that bond to the bonding pads
112
on the semiconductor chip
110
. The beam leads
160
are plated with gold (Au) to improve the bonding quality between the beam leads
160
and the bonding pads
112
. Another Au layer
164
is plated on the solder ball mounting pads
136
, and the solder balls
168
are attached to the Au layer
164
on the solder ball mounting pads
136
. The solder balls
168
are typically a 63% tin (Sn)-37% lead (Pb) alloy.
FIG. 2
depicts the &mgr;-BGA package
200
of
FIG. 1
mounted on a main board
170
. The solder bumps
168
of the package
200
are soldered to pads
172
on the board
170
, typically, in an infrared reflow soldering process in which the soldering process occurs at a maximum temperature of about 220 to 230° C. During the soldering process, Au atoms from the Au layer
164
diffuse into the solder balls and form an intermetallic compound
168
a
with the Sn and Pb atoms of the solder balls. The intermetallic compound
168
a
migrates to the outer surface of the solder bumps
168
and deteriorates the solderability between the solder bumps
168
and the pads
172
on the main board
170
. It would be desirable if the formation of this undesirable intermetallic compound
168
a
could be eliminated.
SUMMARY OF THE INVENTION
In accordance with a first embodiment of the present invention, a method for manufacturing a chip scale package includes: (A) preparing a tape wiring board that comprises a strip of polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the polyimide tape, a window formed in the polyimide tape to enable Cu traces extending across the window to be connected to a semiconductor chip through the window, multiple connection holes formed in the polyimide tape to expose portions the of Cu traces for solder ball attachment, and an elastomer chip carrier attached to the bottom surface of the tape inside of the window; (B) applying a “pre-flux” solution to the portions of the Cu traces exposed through the connection holes to prevent them from being plated with Au; (C) defining beam leads by Au-plating portions of the Cu traces extending across the window; (D) attaching a semiconductor chip to the bottom surface of the elastomer chip carrier such that a peripheral portion of the chip overhangs the carrier and is exposed below the window; (E) bonding the beam leads to the semiconductor chip through the window; (F) encapsulating the bonding area between the beam leads and the semiconductor chip; and, (G) attaching solder balls to the respective portions of the Cu traces exposed through the connection holes.
In steps (B)-(F), the pre-flux used should be thermally stable so that it does not deteriorate prior to effecting solder ball attachment step (G). The step (G) comprises: (G1) placing solder balls on the pre-flux on the Cu traces exposed through the connection holes; (G2) attaching the solder balls to the Cu traces exposed through the connection holes by a reflow soldering process; and; (G3) washing off any remaining pre-flux and other impurity residues around the solder balls.
A second embodiment of the present invention also provides a method for manufacturing a chip scale package. The second method comprises: (A′) preparing a tape wiring board that includes a strip of polyimide tape having top and bottom surfaces, Cu traces formed on the bottom surface of the polyimide tape, a window formed in the polyimide tape to enable Cu traces extending across the window to be connected to a semiconductor chip through the window, multiple connection holes formed in the polyimide tape to expose portions the Cu traces for solder ball attachment, and an elastomer chip carrier attached to the bottom surface of the polyimide tape inside of the window; (B′) attaching a cover film to the top surface of the polyimide tape to prevent the Cu traces exposed through the connection holes from being plated with Au; (C′) Au-plating portions of the Cu traces that are exposed through the window to define beam leads; (D′) removing the cover film from the polyimide tape; (E′) attaching a semiconductor chip to the elastomer; (F′) bonding the beam leads to the semiconductor chip though the window; (G′) encapsulating the bonding area between the beam leads and the semiconductor chip; and, (H′) attaching solder balls to the respective portions of the Cu traces exposed through the connection holes.
In step (B′), the cover film has a window in it corresponding to the window in the polyimide tape to enable the Cu traces extending across the window to be plated with Au to define beam leads. The cover film is preferably an ultraviolet sensitive tape that is made removable by irradiating it with an ultraviolet light. Step (H′) comprises: (H1′) applying a flux to the Cu traces exposed through the connection holes; (H2′) placing solder balls on the flux on the Cu traces exposed through the connection holes; (H3′) attaching solder balls to respective ones of the Cu traces exposed through the connection holes by a reflow soldering process; and, (H4′) washing off any remaining flux and other impurity residues around the solder balls.
REFERENCES:
patent: 4682270 (1987-07-01), Whitehead et al.
patent: 4988395 (1991-01-01), Taguchi et al.
patent: 6114753 (2000-09-01), Nagai et al.
Jeong Do Soo
Lee Dong Ho
Sohn Hai Jeong
Jr. Carl Whitehead
Novacek Christy
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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