Method for forming wordlines having irregular spacing in a...

Details Method for forming wordlines having irregular spacing in a... Method for forming wordlines having irregular spacing in a...

2006-05-30

2006-05-30

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S736000

Reexamination Certificate

active

07052961

ABSTRACT:
According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.

REFERENCES:
patent: 6063547 (2000-05-01), Ye et al.
patent: 6225219 (2001-05-01), Lee et al.
patent: 6818141 (2004-11-01), Plat et al.

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