4. Fishing, trapping, and vermin destroying

Hidehiko Shiraiwa

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Alignment marks with salicided spacers between bitlines for...

Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate

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Alignment system for planar charge trapping dielectric...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate

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Aluminum oxide as liner or cover layer to spacers in memory...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate

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Charge-trapping memory arrays resistant to damage from...

Active solid-state devices (e.g. – transistors – solid-state diode – Mosfet type gate sidewall insulating spacer
Reexamination Certificate

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Dummy wordline for erase and bitline leakage

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1039525

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