Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-29
2003-12-02
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S680000, C438S791000, C438S792000
Reexamination Certificate
active
06656840
ABSTRACT:
BACKGROUND OF THE INVENTION
Sub-half micron multilevel metallization is one of the key technologies for the next generation of very large scale integration (VLSI). Multilevel interconnect structures lie at the heart of this technology. Multilevel interconnect structures are used to link individual transistors in an integrated circuit together.
In recent years, copper has been increasingly used in multilevel interconnect structures. Copper, which has been used as a conductive material in interconnect structures, has advantages over aluminum, which was previously the conductive material of choice. Copper is a better conductor of electricity than aluminum. Better conduction results in faster operating speeds and lower operating voltages. Accordingly, copper has replaced aluminum as the interconnect material of choice in a variety of applications.
“Dual-damascene” processes and barrier layers are used to form copper-based multilevel interconnect structures. In a typical dual-damascene process, a dielectric layer is first etched. Metal is deposited in the etched regions, and excess metal is removed using a planarizing process such as a CMP (“chemical mechanical polishing”) process.
Diffusion barriers are also formed in copper-based interconnect structures. Diffusion barriers are present between the copper structures and the dielectric layers in a multilevel interconnect structure. The diffusion barriers keep the copper in a copper structure from diffusing into the surrounding dielectric layers and into other areas in the multilevel interconnect structure.
Although the use of barrier layers is effective, during fabrication, copper silicide and/or copper oxide films can form when manufacturing multilevel interconnect structures. For example, copper silicide can form between copper and dielectric layers in a multilevel interconnect structure. Residual copper from the CMP process can smear as a result of polishing, and can reside between adjacent copper lines. When a silicon nitride layer is formed on the smeared copper, the silane that is used to form the silicon nitride layer can react with the smeared copper to form copper silicide.
Copper oxide can also form between layers in a multilevel interconnect structure. For example, during fabrication, copper oxide can form on a copper feature after oxygen in the atmosphere oxidizes the surface of the copper feature. If a barrier layer is subsequently formed on the copper feature, copper oxide may reside between the copper feature and the barrier layer in the formed multilevel interconnect structure.
When copper silicide and/or copper oxide reside at the copper/silicon nitride interfaces in a multilevel interconnect structure, problems such as line leakage, electromigration, and stress migration can occur. “Line leakage” is essentially electrical shorting between adjacent conductive structures. Copper silicide and copper oxide films are conductive. Copper silicide residing between adjacent conductive structures may cause or form a leakage path at the dielectric interface. “Electromigration” relates to the diffusion of conductive atoms such as copper within an interconnect structure. The diffusion may be caused by the potential difference between adjacent conductive structures. Copper oxide can form conductive paths between adjacent structures, thus encouraging electromigration. “Stress migration” refers to the mass transport of interconnect material in response to mechanical stress gradients present in the multilevel interconnect structure. The stress gradients result from thermal expansion coefficient mismatches and compliance mismatches between the conductive features and surrounding (e.g., overlying and/or underlying) dielectric materials. Depending on the thermal history, the stress may be either compressive or tensile. Tensile stress can cause void formation, whereas compressive stress can cause hillock formation. Voids continue to grow to reduce the stress until it is energetically unfavorable for them to continue to grow. Migrating voids may also coalesce with other voids thus providing an effective void growth mechanism. The presence of, for example, copper silicide and copper oxide between layers in a multilevel interconnect structure can induce stress in it.
In view of these and other problems, improved microelectronics devices and methods for forming the same are desirable. Embodiments of the invention address the problems described above, as well as other problems, individually and collectively.
SUMMARY OF THE INVENTION
Embodiments of the invention are directed to microelectronics devices and methods for forming the same.
One embodiment of the invention is directed to a method comprising: (a) forming a conductive structure on a substrate; (b) forming a first layer on the conductive structure, wherein the first layer comprises silicon and an element selected from the group consisting of nitrogen and carbon; and (c) forming a second layer on the first layer, wherein the second layer comprises silicon and the element selected from the group consisting of nitrogen and carbon, wherein the atomic ratio of the element to silicon in the first layer is greater than the atomic ratio of the element to silicon in the second layer.
Another embodiment of the invention is directed to a method comprising: (a) forming a copper structure on a semiconductor substrate; (b) removing copper oxide at the surface of the copper structure; (c) forming a first layer comprising silicon and nitrogen on the copper structure; and (d) forming a second layer comprising silicon and nitrogen on the first layer, wherein the nitrogen to silicon ratio in the first layer is greater than the nitrogen to silicon ratio in the second layer, and wherein the second layer is thicker than the first layer.
Another embodiment of the invention is directed to a method comprising: (a) forming a conductive structure on a substrate; (b) forming a first layer on the substrate by reacting a first compound comprising silicon and a second compound comprising an element selected from the group consisting of nitrogen and carbon; and (c) forming a second layer on the substrate by reacting the first compound and the second compound on the first layer, wherein a molar ratio of the second compound to the first compound in (b) is greater than a molar ratio of the second compound to the first compound in (c).
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Feng Joe
Ngai Christopher S
Parikh Suketu A
Rajagopalan Nagarajan
Shek Meiyee (Maggie Le)
Applied Materials Inc.
Jr. Carl Whitehead
Pham Thanhha
Townsend and Townsend and Crew
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