Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-05
2002-08-20
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S570000, C438S637000, C438S653000, C438S680000, C257S384000
Reexamination Certificate
active
06436823
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for fabricating a semiconductor structure and more particularly, relates to a method for forming a TiN layer on a metal silicide layer in a semiconductor structure and a structure formed by the method.
BACKGROUND OF THE INVENTION
In CMOS structures, silicides (TiSi
2
or CoSi
2
) are used as contacts to the active regions as well as for conductive paths between regions of separate devices. In the contact region, a barrier is normally deposited on the silicide in a contact hole to prevent metal and Si inclusion to F attack during the subsequent W deposition from WF
6
. A barrier layer can be formed by depositing Ti on top of the silicide (CoSi
2
) at the bottom of the contact hole and annealing in N
2
/H
2
or NH
3
gas at a temperature between 550° C. and 600° C. to ensure the formation of a TiN or TiON barrier on top of the silicide.
In order to get enough Ti into the bottom of the hole (on top of silicide) of the contacts with higher aspect ratios, ionized metal plasma (IMP) deposition is used. A thick Ti film on top of the silicide ensures better coverage of the barrier layer and reduces the chance of any pin hole in the barrier. However, it was discovered that when a thick (30-60 nm) Ti layer was deposited on top of the silicide layer and annealed at temperatures above 500° C., Ti reacted with CoSi
2
to form an amorphous material between TiON and COSi
2
. The amorphous material contains primarily Ti, Co and Si. The weakly bonded Ti in the amorphous layer can react with fluorine in—WF
6
during the CVD W deposition and form a volatile compound. This volatile compound causes a volume expansion and subsequently results in a barrier liner rupture. The liner rupture exposes the silicide to F attack during CVD WF
6
deposition. This failure mechanism results in an electric open in the W studs.
In addition to the reaction with fluorine, the thick amorphous layer between TiON and CoSi
2
also causes consumption of silicon, which results in a shifting of the silicide layer deeper into the P-well or N-well. The shifting of silicide in to the P or N-well could cause junction leakage.
Due to the consequences of the reaction between F and the amorphous material that contains Ti, Co and Si, it is desirable to either eliminate the formation of the amorphous material layer or to reduce the thickness of the amorphous layer in order to decrease the risk of fluorine attack. TEM (Transmission Electron Microscopy) results on a n as-deposited 35 nm thick Ti film on CoSi
2
after various annealing treatments in forming gas indicated that a 6 nm thick amorphous layer is produced after annealing at 550° C. for 30 min, while an 8 nm thick amorphous layer is obtained after annealing at 600° C. for 30 min. For the 550° C. anneal, the TEM image further shows that Ti amorphizes the top surface of CoSi
2
to form a Ti—Co—Si layer. Neither of these thicknesses, i.e. 6 nm or 8 nm, is acceptable in a high aspect ratio CMOS device. In-situ x-ray diffraction results were obtained on as-deposited 35 nm Ti on CoSi
2
films after various annealing treatments in purified N
2
. The data indicates a thickness reduction in CoSi
2
in contact with Ti as the temperature is increased during N
2
annealing treatments. This result is consistent with the TEM results which show an increased amorphous layer thickness after annealing.
Referring initially to
FIG. 1
, wherein a semiconductor structure
10
is prepared by a conventional method is shown. In structure
10
, a silicon substrate
12
is shown. A native oxide layer
14
is formed on the surface of a metal silicide layer
16
of, for instance, cobalt silicide before the deposition of a titanium layer
18
.
The as-deposited structure
10
is annealed using a conventional annealing method to produce the structure shown in FIG.
2
. After single-step annealing at a high temperature between about 550° C. and about 600° C. for 30 min, on top of the metal silicide layer
16
, a thick amorphous material layer
20
of Ti—Si—Co nitrogen is formed. On top of the amorphous material layer
20
, a Ti—O—N layer
22
is formed. The amorphous material layer
20
formed at a high temperature, i.e. at a temperature higher than 500° C., may have a thickness more than 5 nm, and more likely a thickness between about 5 nm and about 10 nm, as shown in FIG.
5
.
It is therefore an object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer that does not have the drawbacks or the shortcomings of the conventional method.
It is another object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by a suitable annealing process.
It is a further object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure that produces an amorphous material layer of Ti—Co—Si that has a minimum thickness.
It is another further object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by annealing the structure in a dual-step annealing process.
It is still another object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by first forming a sub-stoichiometric TiN at a lower annealing temperature and then forming a stoichiometric TiN layer at a higher annealing temperature.
It is yet another object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure by annealing the structure in a dual-step annealing process consisting of a first step of low temperature annealing at 500° C., and then a second step of high temperature annealing at 600° C.
It is still another further object of the present invention to provide a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure that forms a by-product amorphous material layer of Ti—Co—Si having a thickness of less than 5 nm.
It is yet another further object of the present invention to provide a semiconductor structure that has a TiN layer formed on top of a metal silicide layer which includes an amorphous layer of Ti—Co—Si of less than 5 nm.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and a structure formed by the method are disclosed.
In a preferred embodiment, a method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure can be carried out by the operating steps of first providing a semiconductor structure that has a metal silicide layer on top, depositing a Ti layer on top of the metal silicide layer, depositing a nitrogen-containing Ti layer on top of the Ti layer, heating the semiconductor in a forming gas or nitrogen containing environment to a first temperature not higher than 500° C. for less than 2 hours, and heating the semiconductor structure in an N
2
-containing gas to a second temperature not lower than 500° C. for less than 2 hours to form the TiN layer.
In the method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure, the metal silicide is a member selected from the group consisting of cobalt disilicide, nickel monosilicide, titanium disilicide, tungsten disilicide, tantalum disilicide and niobium disilicide. The ambient gas may be a gas selected from the group consisting of N
2
, NH
3
, N
2
/H
2
. The method may further include the step of heating the semiconductor structure at a first temperature between about 300° C. and about 500° C., and heating the semiconductor structure at a second temperature between about 500° C. and about 800° C. The method may further include the step of heating the semiconductor structure at a first temperature preferably between about 450° C. and about 500° C., and heating the semiconductor structure at
Cabral, Jr. Cyril
Eng Chung-Ping
Gignac Lynne Marie
Lavoie Christian
O'Neil Patricia
Trepp Robert M.
Tung Randy W.
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