Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-03-28
2006-03-28
Lindsay, Jr., Walter L. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S290000
Reexamination Certificate
active
07018901
ABSTRACT:
A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
REFERENCES:
patent: 6124627 (2000-09-01), Rodder et al.
patent: 6638802 (2003-10-01), Hwang et al.
patent: 6838322 (2005-01-01), Pham et al.
patent: 2003/0003620 (2003-01-01), Tanaka
patent: 2003/0032251 (2003-02-01), Chen et al.
patent: WO 02/45156 (2002-06-01), None
Jung, Jongwan et al.; “Implementation of Both High-Hole and Electron Mobility in Strained Si/Strained Si1-yGeyon Relaxed Si1-xGex( x < y ) Virtual Substrate”; IEEE Electron Device Letters; Jul. 2003; pp 460-462; vol. 24, No. 7; IEEE.
Shima, M. et al.; “<100> Channel Strained-SiGe p-MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance”; 2002 Symposium on VLSI Technology Digest of Technical Papers; 2002; pp 94-95; IEEE.
Yen; Yee Chia et al.; “Nanoscale Ultra-Thin-Body Silicon-on-Insulator P-MOSFET with a SiGe/Si Heterostructure Channel”; Apr., 2000; pp 161-163; vol. 21, No. 4; IEEE.
Kim, Sung Min et al.; “Fully Working High Performance Multi-Channel Field Effect Transister (McFET) SRAM Cell on Bulk Si substrate Using TiN Single Metal Gate”; 2005 Symposium of VLSI Technology Digest of Technical Papers; 2005; pp 196-197.
Verheyen P., “25% Drive Current Improvement for p-type Multiple Gate FET (MuGFET) Devices by the Introduction of Recessed Si0.8Ge0.2in the Source and Drain Regions”; 2005 Symposium on VLSI Technology Digest of Technical Papers; 2005; pp194-195.
Kedzierski, Jakub et al.; “Extension and Source/Drain Design for High-Perfornance FinFET Devices”; IEEE Transactions on Electron Devices; Apr., 2003; pp 952-958; vol. 50, No. 4; IEEE.
Choi, Yang-Kyu et al.; “Sub 20nm CMOS FinFET Technologies”; 2001; 4 pgs; IEEE.
Barr Alexander L.
Kolagunta Venkat R.
Nguyen Bich-Yen
Sadaka Mariam G.
Thean Voon-Yew
Balconi-Lamica Michael J.
Freescale Semiconductor Inc.
King Robert I.
Lindsay Jr. Walter L.
LandOfFree
Method for forming a semiconductor device having a strained... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a semiconductor device having a strained..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a semiconductor device having a strained... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3583493