Metal fusion bonding – Process – Preplacing solid filler
Reexamination Certificate
2001-06-14
2003-04-15
Elve, M. Alexandra (Department: 1725)
Metal fusion bonding
Process
Preplacing solid filler
C228S214000, C228S180210, C228S256000
Reexamination Certificate
active
06547124
ABSTRACT:
THE FIELD OF THE INVENTION
This invention relates generally to methods for forming interconnection structures for electronic chips. This invention relates more particularly to a method for forming a micro column grid array (CGA).
BACKGROUND OF THE INVENTION
Two levels of interconnection structures are typically used to join a semiconductor die to a printed circuit board. A first level of interconnection is typically provided between a semiconductor die and a substrate, and then a second level of interconnection is provided between the substrate and the printed circuit board.
One common technique of packaging a semiconductor die is to flip-chip join a semiconductor die to a ceramic substrate. The flip chip approach offers significant advantages in terms of input/output (I/O), packaging density, electrical performance, and manufacturability of a module. A traditional method for achieving a flip chip interconnect is to deposit solder bumps onto an active surface of a semiconductor die. The solder bumps ultimately get reflowed into a spherical shape when making the connection between the semiconductor die and contact pads on a substrate. Electrical traces extend through the substrate to an opposing surface thereof, and connect to an array of solder pads, which are typically spaced apart from each other on a much larger scale than the bumps on the semiconductor die. While this approach has been proven effective, it does have limitations in the achievable I/O contact density, and more significantly, in the reliability of the connections. The reliability issue is due to the fact that a silicon chip and the next level of packaging (e.g., ceramic or organic packaging) experience very different rates of thermal expansion and contraction, and solder has particularly poor fatigue properties.
The problem of differing rates of thermal expansion has been addressed at the board level by attaching components to organic circuit boards with metal columns, which is a form of surface mount technology. Surface mount technology has gained acceptance as a preferred method for joining electronic components to printed circuit boards. Conventional surface mount technology approaches include ball grid arrays (BGAs) and column grid arrays (CGAs). A BGA is an array of spherical solder balls that are attached to a chip, and are used to mount the chip to a printed circuit board. A CGA is an array of cylindrical solder columns that are attached to a chip, and are used to mount the chip to a printed circuit board. The columns offer the same density and performance as a spherical attachment element, but the taller configuration of the solder columns offers compliancy to better absorb the differential thermal expansion rate between the component and the board. The compliancy virtually eliminates the reliability concern caused by the thermal expansion mismatch.
At the wafer level, a technique has been proposed for forming solder columns using solder jetting technology. Such a technique is disclosed in U.S. Pat. No. 6,114,187, issued Sep. 5, 2000, and entitled “METHOD FOR PREPARING A CHIP SCALE PACKAGE AND PRODUCT PRODUCED BY THE METHOD”. In the '187 patent, printing technologies are used to print a package directly onto the semiconductor wafer. The '187 patent notes that the prior art does not print the package directly onto a semiconductor wafer, and that it would be advantageous to build the package directly onto the semiconductor wafer and then divide the wafer into individual semiconductors. The technique disclosed in the '187 patent involves forming solder columns with a solder jetting device that drops successive droplets of solder on top of each other, until the desired column height is reached.
There are several limitations in using solder jetting techniques, such as those disclosed in the '187 patent. First, there are processing speed limitations, in that only one solder column can be formed at a time, unless multiple solder jetting devices are used, which adds to the complexity of the system. Second, it appears that only one wafer can be processed at a time. Third, the repeatability of the process for large-scale fabrication is questionable. The techniques appear to be more appropriate for small, custom applications.
It would be desirable to provide a unique method of forming solder columns using wafer-level processing, without the complexity or limitations of solder jetting technology.
SUMMARY OF THE INVENTION
One form of the present invention provides a method of forming a plurality of micro column interconnection structures on a semiconductor. A semiconductor layer is provided. A photoresist layer is formed on the semiconductor layer. A plurality of cavities are etched in the photoresist layer. The plurality of cavities extend through the photoresist layer to the semiconductor layer. Solder is deposited in the plurality of cavities, thereby forming a plurality of micro columns of solder.
Another form of the present invention provides a method of preparing a chip scale package. A microelectronic device having a connection surface is provided. A photoresist layer is formed on the connection surface of the microelectronic device. A plurality of cavities are formed in the photoresist layer. The plurality of cavities extend through the photoresist layer to the connection surface. Solder is deposited in the plurality of cavities, thereby forming a plurality of solder columns on the connection surface.
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Pomerene Andrew TS
Shah Tushar T.
Sturcken Keith K.
Wright Steven J.
Bae Systems Information and Electronic Systems Integration Inc.
Dicke Billig & Czaja, PLLC
Elve M. Alexandra
Tran Len
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