Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

2001-06-29

2003-04-08

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S212000, C438S240000, C438S253000, C438S259000, C438S268000, C438S270000

Reexamination Certificate

active

06544833

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a manufacturing method of the device.
In recent years, a memory device (ferroelectric memory) has been developed in which a ferroelectric film is used as a memory medium in a capacitor and a field effect transistor is used as a switching element, and has partially been brought to a practical use. The ferroelectric memory is a nonvolatile memory utilizing a phenomenon in which a ferroelectric material generates a potential difference by spontaneous polarization and keeps this state even in no voltage applied state. Even after a power is turned off, a stored content is not lost. Additionally, when the ferroelectric film is sufficiently thin, the spontaneous polarization is reversed fast, and high-speed writing/reading is possible like DRAM.
The ferroelectric memory has the aforementioned characteristics, but Pb(Zr, Ti)O
3
or SrBi
2
Ta
2
O
7
for general use as the ferroelectric film mainly contains low-melting-point metals such as lead and bismuth, the film is therefore unstable, and it is difficult to achieve a thin film. Another problem is that the film is deteriorated in a silicon process, and the ferroelectric memory cannot fulfill its ability.
On the other hand, the ferroelectric film of BaTiO
3
is stable from a viewpoint of thermodynamics, can therefore be thinned, and is not deteriorated even in the silicon process. However, since the Curie temperature thereof is low, a ferroelectric property is not constant and is insufficient.
Furthermore, when BaTiO
3
is epitaxially grown on an underlayer, and lattice mismatching with the underlayer is utilized to introduce strain, a very satisfactory ferroelectric property can be obtained. That is, when stable BaTiO
3
can be used as a ferroelectric material to form an epitaxially grown capacitor on the underlayer, an ideal ferroelectric memory can be realized.
On the other hand, for a capacitor which is used in DRAM and the like, and which mainly includes a paraelectric film such as a silicon oxide film, even when a structure is not of a single crystal, a sufficient capacitor property can be achieved. Therefore, when an interlayer insulating film is formed on a transistor formed on the surface of a semiconductor substrate, and a paraelectric capacitor can directly be formed on the interlayer insulating film in DRAM, a multilayered structure can easily be realized. Therefore, the DRAM can easily and highly be integrated.
However, the epitaxial capacitor for use in the ferroelectric memory cannot be obtained by epitaxial growth directly on the amorphous interlayer insulating film, and it is essential to utilize a single-crystal Si surface as the underlayer in some way. For example, the epitaxial capacitor can be formed in the same surface of the single-crystal Si substrate as a surface with a transistor formed thereon to constitute a memory cell. Of course, in this case, a space of an element region for one bit is twice or more the space of a multilayered structure, and this structure is unsuitable for high integration.
In consideration of the aforementioned respects, various proposals of a multilayered and highly integrated ferroelectric memory have been presented.
As one of the proposals, there is a method (U.S. Pat. No. 5,739,563) comprising: forming the interlayer insulating film for coating the transistor on the Si substrate with the transistor formed beforehand thereon; forming an opening (contact hole) in the interlayer insulating film on either a source electrode or a drain electrode of the transistor; forming a single-crystal Si storage node in the opening by selective epitaxial growth from a vapor phase or epitaxial growth of a solid phase from an amorphous structure; and subsequently forming the epitaxial capacitor on the single-crystal Si storage node by the epitaxial growth.
Since the epitaxial capacitor can be formed on the transistor by this method, the method is suitable for high integration rather than the method of forming the transistor and capacitor laterally on the same Si substrate plane. However, for a higher integration, a smaller contact hole has to be formed on either the source electrode or the drain electrode of the transistor, an aspect ratio of a contact hole depth to width increases, and it is presumed to be difficult to form silicon in a single crystal state in the contact hole.
To avoid this problem, it is proposed to utilize a silicon selective growth property such that selectivity is enhanced at a higher growth temperature and to form single-crystal silicon by higher-temperature growth. However, the substrate temperature cannot be raised to be not less than a range of 750 to 800° C. because of heat resistance of the transistor, and this limits formation of the single-crystal silicon. From this viewpoint, a growth condition for selectively and epitaxially growing the single-crystal Si storage node at a high aspect ratio is very strict. Therefore, in consideration of a yield in preparing several tens of mega or more plugs in one memory device, it is expected that a technical problem to be solved is large.
Moreover, as another preparing method, a method of attaching a first silicon substrate with the epitaxial capacitor formed thereon to a second silicon substrate with the transistor formed thereon is proposed (Japanese Patent Application Laid-Open No. 11-74477). However, when an impact applied to the transistor or the epitaxial capacitor during attachment of the substrates, precision in re-polishing the substrate, and variation of properties among bits, and the like are considered, the technical problem to be solved is also large.
BRIEF SUMMARY OF THE INVENTION
The present invention has been developed to solve the aforementioned problem, and an object thereof is to provide a manufacturing method of a semiconductor memory device in which an epitaxial capacitor can be formed on an upper source/drain region of a vertical field effect transistor in a self-aligning manner, and an inventive semiconductor memory device manufactured by this manufacturing method.
To achieve the object, according to a first aspect of the present invention, there is provided a semiconductor memory device comprising:
a substrate having a main surface;
a single-crystal semiconductor layer having a first conductivity type formed on the main surface of the substrate;
a first impurity region and a second impurity region each having a second conductivity type and formed in the single-crystal semiconductor layer, and spaced from each other in a substantially perpendicular direction to the main surface of the substrate;
a channel portion located between the first impurity region and the second impurity region;
a gate insulating film formed on a surface of the single-crystal semiconductor layer along the channel portion;
a gate electrode formed on the gate insulating film, opposite to the channel portion; and
a capacitor comprising a stacked layer of a lower capacitor electrode layer, a ferroelectric film and an upper capacitor electrode layer, successively and epitaxially grown in this order on the first impurity region.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
a substrate having a main surface;
a single-crystal semiconductor layer formed on the main surface of the substrate;
a plurality of semiconductor columnar portions selectively formed in a surface of the single-crystal semiconductor layer;
a first impurity region formed on each top of the plurality of columnar portions;
a channel portion formed in each of the plurality of semiconductor columnar portions and adjoining to the first impurity region;
a second impurity region formed on the single-crystal semiconductor layer adjoining to a lower portion of each of the plurality of columnar portions, the first impurity region and the second impurity region constituting source and drain regions;
a gate insulating film formed on a side surface of each of the columnar portions;
a gate electrode formed on the side surface o

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