Method for detecting faults in electronic devices, based on...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S025000, C702S064000, C324S523000

Reexamination Certificate

active

07315974

ABSTRACT:
The present invention is related to a method for testing a micro-electronic device, by applying a plurality of test vectors to said device, and measuring for each test vector, the quiescent supply current IDDQ, to said device, wherein each IDDQmeasured value is divided by another IDDQvalue, and wherein the result of said division is compared to a predefined reference, resulting in a pass or fail decision for said device.

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patent: 6342790 (2002-01-01), Ferguson et al.
patent: 6812724 (2004-11-01), Rao et al.
Maxwell et al., “Current Ratios: A Self-Scaling Technique for Production IDDQ Testing”, ITC Test Conference, 1999, IEEE, pp. 738-746.
Okuda. “Eigen Signatures for Regularity-Based IDDQ testing.” Proceedings of the VLSI Test Symposium 2002, pp. 289-294.
Maxwell et al. “Current Ratios: A Self-Scaling Technique for Production IDDQ Testing.” Proceedings of the International Test Conference ITC'99, paper 28.4, pp. 738-746.
Kruseman et al. “The Future of Delta-IDDQ Testing.” Proceedings of the International Test Conference ITC 2001, paper 4.3, pp. 101-110.

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