Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-24
2004-02-10
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S055000, C257S065000, C257S377000, C257S412000, C257S616000, C257S754000, C257S768000
Reexamination Certificate
active
06690072
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a process and structure for achieving very low silicide contact resistance in a Complementary Metal Oxide Semiconductor (CMOS) device. Specifically, a sacrificial silicon layer is deposited on a doped low barrier SiGe source/drain (S/D) region, followed by deposition of a metal such as cobalt. A precisely-defined annealment forms a silicide interface having vertical self-alignment relative to the underlying SiGe layer.
2. Description of the Related Art
Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) scaling requires the continuous reduction of the gate length, gate dielectric thickness, and higher substrate doping. As these entities improve, the intrinsic device resistance scales below 1000 ohm-&mgr;m, leading to faster devices. However, as these entities scale down in size, the silicide used to contact the source and drain becomes an increasingly limiting factor on device speed as related to the parasitic contact resistance of silicide to silicon in the source/drain (S/D) contacts. This is because minimizing the silicide interface resistivity depends mainly on maximizing the S/D doping level, which is already at saturation level in current CMOS technology.
As devices scale smaller, the contact resistance only increases as the silicide/silicon contact area becomes smaller. Thus, not only in relative terms, but also in absolute terms the contact resistance increases as devices scale below 0.1 &mgr;m, placing a severe limitation on potential device improvement obtained by scaling other parameters.
The problem remains to achieve lower source/drain contact resistance as CMOS devices continue to scale down in size.
SUMMARY OF THE INVENTION
In view of the foregoing problems, drawbacks, and disadvantages of the conventional systems, it is an object of the present invention to provide a structure (and method) for achieving very low silicide source/drain contact resistance in a CMOS device.
It is another object of the present invention to form CoSi
2
immediately adjacent to the SiGe source/drain (S/D), but without consumption of the SiGe resulting in a single-phase contact microstructure (i.e., vertically self-aligned with the underlying SiGe layer).
It is still another object of the present invention to provide a simple process to form a low resistance contact to low band-gap SiGe devices, thereby to provide lower resistance than conventional Si S/D CMOS where the band-gap is higher.
It is still another object of the present invention to overcome the problem of reaction of metal with SiGe which forms undesirable multiphase microstructure by using a sacrificial Si overlayer within which to form the silicide.
It is still another object of the present invention to teach, for ease of manufacturing, a wide process window in terms of Co metal thickness and Si layer thickness in which the process of the present invention will work.
It is still another object of the present invention to teach, also for ease of manufacturing, a wide process window in terms of the annealing temperature to form CoSi
2
.
In a first aspect of the present invention, a method is described herein of forming a vertically self-aligned silicide contact to an underlying SiGe layer, including formation of a layer of silicon of a first predetermined thickness on the SiGe layer and formation of a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal at a first predetermined temperature selected from a temperature range having a lower threshold temperature and an upper threshold temperature. The lower threshold temperature comprises a temperature at which the silicon layer interacts with the metal layer to form the first silicide. The upper temperature threshold comprises a temperature at which the first silicide forms from silicon atoms from the SiGe layer.
In a second aspect of the present invention, a method is described herein of forming a silicide contact for a metal-oxide semiconductor (MOS) transistor, the MOS transistor comprising a source, a drain, and a gate structure on a layer of SiGe, including forming a layer of silicon of a first predetermined thickness in a region to have the silicide contact, applying a layer of metal over the silicon, a thickness of the metal layer being a second predetermined thickness, and providing a thermally annealing process at a predetermined temperature, thereby forming a siliside of the silicon and metal, where the predetermined temperature is chosen to substantially inhibit penetration of the silicide into the underlying SiGe layer.
In a third aspect of the present invention, a structure of a MOSFET (Metal Oxide Semiconductor Transistor) is described herein, including a source region formed on a layer of SiGe, a drain region formed on a layer of SiGe, and a silicide layer formed over at least one of the source region and the drain region, wherein the silicide layer is essentially vertically self-aligned with the underlying layer of SiGe.
In a fourth aspect of the present invention, described herein is the structure of a silicon-based electronic device including a region of a layer of SiGe and a silicide layer formed over the region, wherein the silicide layer is essentially vertically self-aligned with the underlying layer of SiGe.
The present invention, therefore, provides the method and structure of a vertically self-aligned source/drain silicide contact having the advantages of lowering resistance by using an underlying layer of SiGe to reduce the Schottky barrier height while maintaining low contact resistance characteristic of silicide without the problems typically present with a silicide/SiGe interface
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patent: 5818100 (1998-10-01), Grider et al.
patent: 5955745 (1999-09-01), Yamazaki
patent: 6214679 (2001-04-01), Murthy et al.
patent: 6235568 (2001-05-01), Murthy et al.
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Cabral, Jr. Cyril
Carruthers Roy A.
Chan Kevin K.
Chu Jack O.
Cohen Guy Moshe
Hogans David L.
Jr. Carl Whitehead
McGinn & Gibb PLLC
Salys, Esq. Casimer K.
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