Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-29
2003-01-21
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S729000, C714S731000
Reexamination Certificate
active
06510534
ABSTRACT:
The present invention relates, generally, to the testing of digital systems and circuits and, more specifically, relates to a method for use in testing of high-performance digital systems and circuits and to a test controller for implementing the method.
BACKGROUND OF THE INVENTION
The testing of digital systems and circuits has become a highly advanced art. Generally, integrated circuits include combinational or core logic which perform the functions for which the circuits were designed. Input and output pins are provided for passing signals to and from the core logic from other components. Memory elements are provided in the chip for storing data. Some memory elements, but not necessarily all, are constructed so that the memory elements can be connected in series to form a scan chain and allow a test stimulus to be loaded into the memory elements and response data to be unloaded therefrom for analysis. A built-in test controller is provided for controlling test operations. Tests typically involve loading a test stimulus into the scannable memory elements, operating the circuit in normal mode for at least one cycle of a test clock and then unloading the data from the memory elements for analysis.
In some tests, the test clock is provided by test equipment and is frequently not the clock speed for which the chip or circuit was designed. It is desired to perform at-speed tests of the circuit at all levels of packaging of the circuit, i.e., wafer probe, final test, burn-in, board and system test, etc. One difficulty which requires a solution is the provision of a method for generating capture and shift clocks from free-running clocks in circuits having “clocked scan” type memory elements. Co-pending U.S. patent application Ser. No. 09/430,686 filed on Oct. 29, 1999 for “Method and Apparatus for Testing Circuits with Multiple Clocks”, now U.S. Pat. No. 6,442,722, assigned to the Assignee of the present invention, addresses this problem for circuits containing only scannable memory elements of the “muxed scan” type in which the memory elements are clocked by the same clock during both the shift and capture sequences. However, the method used to implement at-speed testing is not applicable to the “clocked scan” methodology. Other prior art applicable to “clocked scan” methodology, does not address the problem of generating capture and shift clocks from free-running clocks because the clocks are controlled from a tester external to the chip. These previous methods are not applicable when the system clock frequency is too high and the test equipment cannot provide the desired clock because of parasitic effects in the connections between the tester and the circuit under test. An on-chip clock generator providing a free-running clock is more appropriate in this case.
Another situation which requires a solution is the need to re-test the circuit in the system where clocks are typically generated from crystals or other sources that cannot be controlled in a way that is compatible with the shift and capture sequences required by the clocked scan methodology.
A further difficulty that must be overcome is the need to properly initialize a circuit under test which contains non-scannable memory elements. In such an arrangement, the first shift sequence alone is not sufficient to initialize all memory elements and ensure that no unknown values propagate back to the test controller. At the beginning of the test, all memory elements contain an unknown value. The scannable memory elements are initialized by shifting in known values from the test controller. Since the non-scannable memory elements only receive the capture clock, their respective value remains unknown. At the end of the test stimulus loading sequence, a first capture clock is applied to the memory elements. The unknown values contained in non-scannable memory elements propagate through the combinational logic and will cause unknown values to be captured by the scannable memory elements.
Also, the non-scannable memory elements which receive data originating from scannable memory elements will capture known values since their inputs only depend on the output of memory elements that have been initialized. However, if a second capture clock cycle is applied to perform an at-speed test, unknown data will propagate to the non-scannable memory elements. An associated problem relates to “sequential loops”, i.e., non-scannable memory elements whose outputs are connected to their inputs through the combinational logic.
A still further problem relates to performing at-speed tests in absence of the system clock when the system clock is not available as required for diagnostic purposes.
SUMMARY OF THE INVENTION
The present invention seeks to provide a method of testing high performance circuit digital systems and circuits which employ clocked scan type scannable memory elements
One aspect of the present invention relates to a method of testing high performance digital systems and circuit using a free running test clock and a free running system clock. In accordance with this aspect of the invention, there is provided a method of performing an at-speed test of a circuit having combinational logic and scannable, clocked scan type memory elements each scannable memory element having a capture clock input, a shift clock input, the method comprising loading a test stimulus into the scannable memory elements under the control of a shift clock derived from a free running test clock; performing a capture operation under the control of a capture clock derived from one of the free running test clock and a free running system clock for a predetermined number of cycles of the capture clock; and unloading test response data from the scannable memory elements under the control of the shift clock.
Another aspect of the present invention relates to a method for performing at-speed tests of high performance digital systems and circuits using a test clock and a system clock but which is capable of performing a test using only the test clock when the system clock is not available. In accordance with this aspect of the invention, there is provided a method of performing an at-speed test of a circuit having combinational logic and scannable, clocked scan type memory elements each scannable memory element having a capture clock input, a shift clock input, the method comprising configuring the circuit in an active or an inactive debug mode; when the circuit is configured in an active debug mode, loading a test stimulus into the scannable memory elements under the control of a shift clock signal derived from a test clock; performing a capture operation under the control of a capture clock derived from the test clock for a predetermined number of cycles of the capture clock; and unloading test response data from the scannable memory elements under the control of the shift clock signal; and when the circuit is configured in an inactive debug mode, loading a test stimulus into the scannable memory elements under the control of a shift clock signal derived from a test clock; performing a capture operation under the control of a capture clock derived from one of the test clock and a system clock for a predetermined number of cycles of the capture clock; and unloading test response data from the scannable memory elements under the control of the shift clock signal.
A further aspect of the present invention relates to a method of testing high performance digital systems and circuits which include non-scannable memory elements. In accordance with this aspect of the invention, there is provided a method of performing an at-speed test of a circuit having combinational logic and scannable, clocked scan type memory elements each scannable memory element having a capture clock input, a shift clock input, the method comprising configuring the circuit in an active or an inactive initialization mode; when the circuit is configured in an active initialization mode, iteratively loading initialization data into the scannable memory elements and then performing a capture cycle under the
Burek Dwayne
Cote Jean-Francois
Maamari Fadi
Nadeau-Dostie Benoit
LogicVision, Inc.
Moise Emmanuel L.
Sheridan & Ross P.C.
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