4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Jean-Francois Cote

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Asynchronous interface

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Patent

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Hierarchical design and test method and system, program...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Method and apparatus for controlling power level during BIST

Electrical computers and digital processing systems: support – Computer power control – Power conservation
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Method and apparatus for high-speed interconnect testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for testing high performance circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Profile ID: LFUS-PAI-P-1034811

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