Method and apparatus for semiconductor device with improved...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S199000, C438S217000, C438S218000, C438S305000, C438S353000, C438S514000, C438S524000, C257SE21431, C257SE21507

Reexamination Certificate

active

07364957

ABSTRACT:
A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.

REFERENCES:
patent: 4788160 (1988-11-01), Havemann et al.
patent: 5516711 (1996-05-01), Wang
patent: 5972762 (1999-10-01), Wu
patent: 5998839 (1999-12-01), Cho
patent: 6017801 (2000-01-01), Youn
patent: 6165880 (2000-12-01), Yaung et al.
patent: 6191462 (2001-02-01), Chen-Hua
patent: 6207519 (2001-03-01), Kim et al.
patent: 6329257 (2001-12-01), Luning et al.
patent: 6368926 (2002-04-01), Wu
patent: 6498067 (2002-12-01), Perng et al.
patent: 6642122 (2003-11-01), Yu
patent: 6747373 (2004-06-01), Hu et al.
patent: 6870179 (2005-03-01), Shaheed et al.
patent: 6911376 (2005-06-01), Yoo
patent: 6914309 (2005-07-01), Koga
patent: 2002/0048898 (2002-04-01), Li
patent: 2003/0073270 (2003-04-01), Hisada et al.
patent: 2004/0063289 (2004-04-01), Ohta
patent: 2005/0258515 (2005-11-01), Chidambarrao et al.
patent: 2006/0231826 (2006-10-01), Kohyama
Thompson, S., et al., “MOS Scaling: Transistor Challenges for the 21st Century,” Intel Technology Journal Q3'98, pp. 1-19.
Ge, C.-H., et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” IEDM, IEEE, 2003, pp. 73-76.
Thompson, S. E., et al., “A 90-nm Logic Technology Featuring Strained-Silicon,” IEEE Transactions on Electron Devices, vol. 51, No. 11, Nov. 2004, pp. 1790-1797.

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