Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2007-01-09
2010-02-02
Butler, Dennis M (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000, C711S167000
Reexamination Certificate
active
07657771
ABSTRACT:
Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.
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PCT Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration, Mar. 25, 2008, 10 pages.
Allen, Jr. James J.
Jenkins Steven K.
Mossman James A.
Trombley Michael R.
Butler Dennis M
International Business Machines - Corporation
McBurney Mark E.
Yee & Associates P.C.
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