Michael R. Trombley

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Data bus bandwidth scheduling in an FBDIMM memory system...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate

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Error control coding methods for memories with subline accesses

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Independent control of DMA and I/O resources for mixed-endian co

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Memory system with apparatus and method to enable balanced...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
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Method and apparatus for reducing latency associated with...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
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Profile ID: LFUS-PAI-P-1731454

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