Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-12
2007-06-12
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000
Reexamination Certificate
active
11122237
ABSTRACT:
A multi-level scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain including one or more scan cells coupled in series. Two or more decompressors are embedded between N compressed scan inputs and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N compressed scan inputs into decompressed scan data patterns stored in the M scan chains. The multi-level scan compression approach allows to speed up the shift-in/shift-out operation during decompression using two or more decompressors separated by intermediate scan chains. Two or more compressors are separated by intermediate scan chains to speed up the shift-in/shift-out operation during compression.
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Abdel-Hafez Khader S.
Sheu Boryau (Jack)
Wang Laung-Terng (L.-T.)
Wu Shianling
Kerveros James C
Syntest Technologies, Inc.
Zegeer Jim
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