Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With electrical contact in hole in semiconductor
Reexamination Certificate
2011-06-28
2011-06-28
Bryant, Kiesha R (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With electrical contact in hole in semiconductor
C257SE23174, C257SE21597, C438S667000
Reexamination Certificate
active
07968975
ABSTRACT:
An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
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U.S. Appl. No. 11/328,939 entitled “Method and System of Using Artifacts to Identify Elements of a Component Businness Model”, filed on Jan. 10, 2006, First Named Inventor: David Bernard Flaxer.
International Search Report dated Sep. 22, 2009.
Collins David S.
Joseph Alvin
Lindgren Peter J.
Stamper Anthony K.
Watson Kimball M.
Bryant Kiesha R
International Business Machines - Corporation
Schnurmann H. Daniel
Scully , Scott, Murphy & Presser, P.C.
Wright Tucker
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