Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-07-12
2001-01-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S201000
Reexamination Certificate
active
06175524
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit devices, and more particularly to Merged Memory and Logic (MML) integrated circuit devices and methods of testing the same.
BACKGROUND OF THE INVENTION
Integrated circuit devices, such as integrated circuit memory devices and integrated circuit logic devices, are widely used in consumer and commercial applications. Recently, Merged Memory and Logic (MML) integrated circuit devices have been developed. MML integrated circuit devices generally include a large capacity memory and a large logic block that are merged in one integrated circuit device. Thus, an MML integrated circuit device can replace discrete memory and logic chips that are used in personal computers and other consumer and commercial devices. MML devices are described, for example, in U.S. Pat. No. 5,848,016 to Kwak, entitled “Merged Memory and Logic (MML) Integrated Circuits and Methods Including Serial Data Path Comparing”, and assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference.
MML integrated circuit devices may present new challenges for the testing thereof. In particular, an MML integrated circuit device generally provides a large number of internal data paths between the memory block and the logic block. For example, up to 256 or more internal data paths may be provided. Since many of these internal data paths are not brought out to external MML integrated circuit device pads, it may be difficult to access all of the internal data paths in order to test the memory block.
Stated differently, in order to test a conventional memory integrated circuit device, test equipment is coupled to the pads of the memory integrated circuit device. However, the memory block in an MML integrated circuit device may be difficult to test because the memory is connected to the external pads through the logic block.
It is also known to provide MML integrated circuit devices that include a buffer memory, generally having a smaller capacity than the memory block. The buffer memory is connected to the memory block and generally operates at a higher speed than the memory block. For example, the memory block may be a Dynamic Random Access Memory (DRAM) and more preferably a synchronous DRAM, and the buffer memory may be a Static Random Access Memory (SRAM). The buffer memory operates as a buffer between the memory block and the logic block. Thus, the memory block transmits and receives data only to and from the buffer memory. The logic block also transmits data to and receives data from the buffer memory.
In an MML integrated circuit device that includes a buffer memory between a memory block and a logic block, it may be difficult to test the memory block. In particular, in a conventional integrated circuit memory device, the memory cells of the memory device may be tested by directly accessing the memory from external of the integrated circuit memory device. It is known to use a multiplexer to select different modes, such as a normal operation mode, an external test mode and a Built-In Self-Test (BIST) mode, to directly access the memory.
In an MML integrated circuit device, when there are a large number of input and output data buses for the memory block, a large number of data buses may need to be added between the memory block and the buffer memory for normal operation and between the BIST circuit and the memory block for self-test. Moreover, a large number of data buses may need to be added between the multiplexer and the memory block in order to directly access the memory block from outside the MML integrated circuit device. The addition of these buses may unduly increase the size of the MML integrated circuit device. Moreover, it may be difficult to test the performance of the memory block during its normal operation when it is communicating only with the buffer memory.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved MML integrated circuit devices.
It is another object of the present invention to provide MML integrated circuit devices that need not unduly increase the area thereof to accommodate buses for testing.
It is still another object of the present invention to provide MML integrated circuit devices and methods of testing thereof that can detect errors in the memory block thereof when the memory block communicates with the logic block through a buffer memory.
These and other objects are provided, according to the present invention, by an MML integrated circuit device that includes a memory block, a logic block and a buffer memory, and a selection circuit that is coupled between the logic block and the buffer memory. The selection circuit is responsive to external data and to the logic block, to transmit the external data or data from the logic block to the memory block via the buffer memory. Thus, MML integrated circuit devices according to the invention can use the buffer memory to access the memory block during a normal operational mode and during a test mode.
MML integrated circuit devices according to the invention also preferably include a Built-In Self-Test (BIST) block that is coupled to the selection circuit to transmit BIST data to the memory block via the buffer memory. The selection circuit preferably includes a plurality of multiplexers, a respective one of which is coupled to the external data, to the logic block and to the BIST block.
The buffer memory generally is of smaller size than the memory block. MML integrated circuit devices according to the present invention preferably include a data expansion circuit that is coupled between the external data and the selection circuit, to replicate the external data a predetermined number of times and to transmit the replicated external data to the selection circuit.
A second selection circuit also may be included that is responsive to parallel data from the buffer memory, to sequentially select portions of the parallel data from the buffer memory and to sequentially output the selected portions of the parallel data to external of the MML integrated circuit device. A third selection circuit also may be included that is coupled to the logic circuit and to the second selection circuit, to select the output of the logic circuit or the sequentially selected portions of the parallel data from the second selection circuit, for output external of the MML integrated circuit device.
Errors may be detected in an MML integrated circuit device that includes a memory block, a logic block and a buffer memory, by storing external data from external of the MML integrated circuit device into the buffer memory, and storing the external data from the buffer memory into the memory block. The external data is read from the memory block and the read external data is stored from the memory block into the buffer memory. The read external data is output from the buffer memory to external of the MML integrated circuit device. The external data may be stored from external of the MML integrated circuit device into the buffer memory by applying external data from external of the MML integrated circuit device to the MML integrated circuit device, replicating the external data a predetermined number of times in the MML integrated circuit device and storing the replicated external data in the buffer memory.
The step of storing external data from external of the MML integrated circuit device into the buffer memory may be repeatedly performed to fill the buffer memory with the external data. Moreover, the step of storing the external data from the buffer memory into the memory block may be repeatedly performed to fill the memory block with the stored external data from the buffer memory. In order to output the read external data from the buffer memory to external of the MML integrated circuit device, portions of the read external data are sequentially selected from the buffer memory. The selected portions of the read external data are sequentially output to external of the MML integrated circuit device. Accordingly,
Dinh Son T.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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