Memory with improved charge-trapping dielectric layer

Details Memory with improved charge-trapping dielectric layer Memory with improved charge-trapping dielectric layer

2006-07-11

2006-07-11

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S954000

Reexamination Certificate

active

07074677

ABSTRACT:
A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is deposited.

REFERENCES:
patent: 5963833 (1999-10-01), Thakur
patent: 6136728 (2000-10-01), Wang
patent: 6248628 (2001-06-01), Halliyal et al.
patent: 6284583 (2001-09-01), Saida et al.

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