Memory repair circuit using antifuse of MOS structure

Details Memory repair circuit using antifuse of MOS structure Memory repair circuit using antifuse of MOS structure

2000-12-18

2002-11-05

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S225700

Reexamination Certificate

active

06477094

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory repair circuit; and, more particularly, to an antifuse of MOS structure and a memory repair circuit using the antifuse.
PRIOR ART OF THE INVENTION
According to development of the semiconductor integrated circuit, more circuit devices is included in a given silicon area. On the other hand, in order to reduce or eliminate defects in the circuit devices, more circuit devices are required. Circuit designers make efforts to decrease size of the individual circuit to accomplish higher integration by maximizing die usage ratio. Such down-sizing makes the circuit devices influenced by defects due to contaminant during manufacturing. The defect should be detected during a test procedure performed after integrated circuit manufacture step or semiconductor chip level or package completion. When the defect is detected, especially, a small number of circuit devices has substantially the defect, it is not desirable to throw out the integrated circuit having the defective circuit device.
Since zero defect in manufacture of the integrated circuit cannot be expected, a redundant circuit is provided to reduce the thrown integrated circuit. When a first device is determined as defective one, the redundant circuit replaces the first device. Substantial reduce of the thrown integrated circuit can be accomplished by the redundant circuit device without increase of cost of the integrated circuit.
For example, there are DRAM, SRAM, VRAM and EPROM among the integrated circuit using the redundant circuit device. The typical integrated memory circuit includes a multiplicity of memories disposed at an array of addressable rows and columns. Each of the memories at the rows and columns is the first circuit device. By providing the redundant circuit device, a first row, column or bit that is defective can be replaced.
Since the first circuit device of the individual integrated memory circuit can be addressable separately, fuse blowing or an antifuse of a fuse control programmable circuit for programming the redundant circuit depending on the address of the defective first circuit device is required to replace the defective device. This procedure is very effective in replacement of the defective device permanently.
For example, for the DRAM, a particular cell is selected by providing the address for the row and column at which the particular cell is located. The redundant circuit should perceive the valid first memory circuit device and, when the address for the first circuit device is provided by a user, all signals should be changed for the redundant circuit device. Accordingly, a number of the fuses or antifuses are coupled to the corresponding redundant circuit device. A possible combination of blown or unblown fuses corresponding to the redundant circuit devices represents a single address of all of the first devices to be replaced by the corresponding redundant device.
The antifuse is a device coupling two electrodes by using dielectric breakdown of electrode/insulator/electrode structure. Dielectric breakdown voltage of the insulator is referred as a program voltage (PGM) of the antifuse, at which the two electrodes are shorted by a program.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a memory repair circuit using an antifuse of MOS structure, capable of repairing defective cells by constructing the antifuse by MOS transistors and programming the antifuse circuit properly.
In accordance with an aspect of the present invention, there is provided a memory repair circuit comprising: a plurality of antifuse devices, each programmed when a power voltage and a negative voltage are supplied respectively to a first electrode and a second electrode thereof; a latching means for detecting and latching program states of the antifuse devices; and a redundancy block for replacing a defect cell with a redundancy cell depending on the output of the latching means.
In accordance with an aspect of the present invention, there is provided a memory repair circuit comprising: a power-up reset circuit for outputting a power voltage when the power transits from 0 V to a predetermined voltage; an address multiplexer for outputting a signal for selecting a fuse to program; a voltage generator for supplying a program voltage; an antifuse circuit for programming an antifuse device depending on outputs of the power-up reset circuit, the address multiplexer and the voltage generator and sensing whether the antifuse device is programmed; and a redundancy block for replacing a detective cell with a redundancy cell depending on the output of the antifuse circuit.


REFERENCES:
patent: 5831923 (1998-11-01), Casper
patent: 5844298 (1998-12-01), Smith et al.
patent: 6108261 (2000-08-01), Kim et al.
patent: 6125069 (2000-09-01), Aoki

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