Memory cell configuration and corresponding fabrication method

Details Memory cell configuration and corresponding fabrication method Memory cell configuration and corresponding fabrication method

1999-02-12

2001-07-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S386000

Reexamination Certificate

active

06258658

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor field. Specifically, the present invention relates to a memory cell configuration with a multiplicity of preferably ferroelectric memory cells provided in a semiconductor substrate (ferroelectric memory (FeRAM) or nonvolatile random-access memory (NVRAM)) and to a corresponding fabrication method.
Although applicable to memories made of any desired base material, the present invention and also the problems on which it is based are explained with regard to a silicon-based memory.
In general, a DRAM memory is formed from a memory cell configuration whose individual memory cells have a selection transistor and a capacitor connected thereto. A memory cell of a ROM memory consists of only a transistor.
In the beginning, memory cell configurations were based on predominantly planar designs. With the stipulation of a constantly increasing packing density, a proposal has already been made for mask ROM applications (read-only memory) which envisages folding the cell area of the memory by introducing parallel longitudinal trenches and thus reducing the cell area when projected onto the wafer surface by up to 50%. The utilization of the vertical direction in the form of capacitances as trench or stacked capacitor is known in the case of DRAMs.
German patent DE 195 14 834 discloses a read-only memory cell configuration having first memory cells with a vertical MOS transistor and second memory cells without a vertical MOS transistor. The memory cells are arranged along opposite sidewalls of mutually parallel strip-type insulation trenches. If the width and spacing of the insulation trenches are chosen to be identical, then the minimum space requirement per memory cell is theoretically 2F
2
, where F is the minimum structure size of the manufacturing technology.
German published patent application DE 195 10 042 discloses a read-only memory cell configuration in which the memory cells are arranged in parallel rows. Longitudinal trenches run essentially parallel to the rows. In this case, the rows are respectively arranged alternately on the main area between neighboring longitudinal trenches and on the bottom of the longitudinal trenches. Insulation structures are provided for mutual insulation of the memory cells, which each comprise a MOS transistor. Word lines run transversely with respect to the rows and are each connected to the gate electrodes of MOS transistors arranged along different rows. In this case, the minimum space requirement per memory cell is theoretically 4F
2
, where F is the minimum structure size of the respective technology.
The commonly assigned, copending application No. 08/755,456, which corresponds to the German published patent application DE 195 43 539, discloses a RAM memory cell configuration having a vertical storage capacitor with a ferroelectric or paraelectric storage dielectric. In order to fabricate the storage capacitor, a dielectric layer for the storage dielectric is produced in a large-area manner. The dielectric layer is subsequently structured, and first and second electrodes are formed for the storage capacitors.
The storage dielectric used in accordance with the disclosure of the copending application is ferroelectric material for nonvolatile memories, since that material has spontaneous polarization which is present even in the absence of an external electric field. Paraelectric material, on the other hand, is used in DRAM applications, in which a refresh cycle is provided.
In practice, however, the known designs for memory cells comprising a selection transistor and a storage capacitance (for example DRAM) at present only enable cell sizes for a memory cell of 9.6 F
2
. The aim is a cell size of 8 F
2
starting with the 1 Gb generation, where F=0.18 &mgr;m.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration having preferably ferroelectric memory cells, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which can be fabricated simply and reliably. It is a further object to provide a corresponding fabrication method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, comprising:
a semiconductor substrate having a main surface with a multiplicity of, preferably ferroelectric, memory cells;
a plurality of mutually parallel bit line trenches extending in a longitudinal direction in said main surface of said semiconductor substrate, said bit line trenches having bottoms with respective bit lines provided therein, crowns formed with respective source/drain regions, and walls with respective channel regions;
wherein said channel region on a first wall of a respective said trench forms a drivable selection transistor of a respective one of said memory cells, and said channel region on a second wall forms a closed transistor;
insulated word lines for driving said selection transistors extending in a transverse direction along said main surface of said semiconductor substrate through said bit line trenches;
insulation trenches extending in the transverse direction along said main surface of said semiconductor substrate, said insulation trenches insulating said source/drain regions of longitudinally adjacent memory cells; and
a plurality of capacitors each connected to said source/drain region of a respective memory cell and disposed above said word lines.
The inventive memory cell configuration having ferroelectric memory cells has the advantage over known memory cell configurations that it has an achievable minimum cell size of 6 F
2
.
In contrast to the customary method for fabricating a DRAM with a stacked capacitor, the bit line in the memory cell configuration according to the invention is no longer situated between source/drain region and capacitor. This means that the aspect ratio for the contact plug, which provides for the connection of the capacitor to the selection transistor, is distinctly relaxed. In order to connect the bit line, the same is passed up with a diffusion contact to the original level of the semiconductor substrate, with the result that here, too, a relaxed aspect ratio is produced for the contact holes. The contact plugs can be embodied in a self-aligned manner. Otherwise, it is likewise possible to have recourse exclusively to customary process steps.
The idea on which the present invention is based consists in implementing the selection transistor as a vertical transistor on a trench wall, the opposite trench wall being configured in such a way that the transistor located there is always closed, that is to say its threshold voltage is beyond the supply voltage. The planar base area for the ferroelectric capacitance is 2 F
2
. This size can be realized without any technical difficulties in the fabrication method specified. A further increase in the capacitor area can be obtained by utilizing the side areas of the lower electrode.
In accordance with an added feature of the invention, the respective channel region of the wall opposite the selection transistor is doped in such a way that the transistor located there is always closed, that is to say its threshold voltage is beyond the supply voltage. In this way, it is possible to define a selection transistor by way of the channel doping, that is to say by way of the definition of the threshold voltage.
In accordance with an additional feature of the invention, an oxide layer is provided between the source/drain regions and the channel regions, on the one hand, and the respective word line on the other hand. In this way, it is possible to obtain good electrical insulation of the word lines with respect to the source/drain regions and the channel regions.
In accordance with another feature of the invention, the word lines have laterally insulating spacers made of silicon oxide or silicon nitride.
In accordance with a further preferred development, the word lines have an insulating space

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