4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Brian King Flachs

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Condition code register architecture for supporting multiple...

Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate

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Lowered PU power usage method and apparatus

Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate

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Memory array manufacturing defect detection system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Memory array manufacturing defect detection system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Memory with combined line and word access

Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
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Profile ID: LFUS-PAI-P-2392778

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