Manufacturing method for semiconductor device to mitigate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S301000, C438S305000, C438S306000, C257SE21437, C257SE21345

Reexamination Certificate

active

07449386

ABSTRACT:
A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a first conductivity type that is the same as that of the substrate, is implanted at first and second angles in both the first and second regions to form halo regions only in source sides under the gate structures in the first region and in both source and drain sides under the gate structures in the second region.

REFERENCES:
patent: 5278078 (1994-01-01), Kanebako et al.
patent: 5739058 (1998-04-01), Karniewicz et al.
patent: 6008093 (1999-12-01), Aoki et al.
patent: 6242329 (2001-06-01), Huster et al.
patent: 6358787 (2002-03-01), Dennison et al.
patent: 6372587 (2002-04-01), Cheek et al.
patent: 6458665 (2002-10-01), Kim
patent: 6503789 (2003-01-01), Kim et al.
patent: 6645806 (2003-11-01), Roberts
patent: 6777351 (2004-08-01), Hill
patent: 6794235 (2004-09-01), Liu et al.
patent: 6940137 (2005-09-01), Chen et al.
patent: 2002/0020891 (2002-02-01), Madurawe et al.
patent: 2003/0124788 (2003-07-01), Roberts
patent: 2003/0209758 (2003-11-01), Lee et al.
patent: 2004/0157397 (2004-08-01), Quek
patent: 2005/0093083 (2005-05-01), Hiraizumi
patent: 2005/0136607 (2005-06-01), Kim
patent: 2005/0142782 (2005-06-01), Kim
Buti et al., “A New Asymmetrical Halo Source Gold Drain (HS-Gold) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance”, IEEE Transactions on Electron Devices, vol. 38, No. 8, pp. 1757-1764, Aug. 1991.
Jung et al., “A 0.25 mu m Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) Using Halo Implantation for 1 Gbit Dynamic Random Access Memory (DRAM)”, Japanese Journal of Applied Physics, Part. 1 (Regular Papers & Short Notes), vol. 35, No. 2B, pp. 865-868, Feb. 1996. (Abstract only).
Miyamoto et al., “An Asymmetrically Doped Buried-Layer (ADB) Structure for Low-Voltage Mixed Analog-Digital CMOS LSI's”, IEEE Transactions on Electron Devices, vol. 46, No. 8 pp. 1699-1704, Aug. 1999.
Hook et al., “High-Performance Logic and High-Gain Analog CMOS Transistors Formed by a Shadow-Mask Technique with a Single Implant Step”, IEEE Transaction on Electron Devices, vol. 49, No. 9, pp. 1623-1627, Sep. 2002.
Lenbole et al., “Impact of Tilt Angle Variation on Device Performance”, 2002 14thInternational Conference on Ion Implantation Technology Proceedings, pp. 44-47, 2003.
Zhao et al., “Ion Implantation Angle Variation to Device Performance and the Control in Production”, AIP Conference Proceedings, vol. 680, No. 1, pp. 666-669, Aug. 26, 2003.
Genshu, “The Ion Implantation Equipment”, Denshi Zairyo (Electronic Parts and Materials), 12 gatsugo bessatsu, pp. 112-117, 2004. (Abstract only).

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