Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-15
2002-04-30
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S624000, C438S792000
Reexamination Certificate
active
06380014
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a manufacture method of semiconductor devices, and more particularly to a manufacture method of semiconductor devices having fine MOS transistors.
b) Description of the Related Art
High integration and high speed are requisites for improvement on the performance of semiconductor integrated circuit devices. Therefore, MOS transistors which are typical semiconductor elements of integrated circuit devices are required to be made fine or small. Sizes of a MOS transistor are becoming small both in substrate surface and depth directions, e.g., a gate oxide film of 10 nm or thinner and a source-drain junction of 100 nm or shallower.
As MOS transistors are made fine, impurities are re-distributed during thermal processes to cause the short channel effect (punch-through between the source and drain), or impurities in the gate electrode penetrate through the gate oxide film into the channel region. In order to solve these problems, it is generally required to use low temperature processes.
An interlayer or interlevel insulating film has been formed mostly by batch thermal CVD after a gate electrode and source/drain regions on both sides of the gate electrode are formed. To meet the need of low temperature processes, technology of forming an interlayer insulating film by plasma CVD (PECVD) or technology of forming it by single wafer processing type thermal CVD have been developed. It is sufficient for a substrate to be heated to about 300° C. to 550° C. during plasma CVD.
Dual-gate surface channel MOSFETs, with p-type impurities such as B being doped in the gate electrode of a p-channel transistor and n-type impurities such as P and As being doped in the gate electrode of an n-channel transistor, are now being used to realize high performance of CMOS transistors.
In order to form a low resistance contact to a small area of a semiconductor surface, silicide (salicide) techniques are used to form in a self-alignment manner a silicide (salicide) layer on the surface of a source/drain region (in some cases, also on a gate electrode). Incorporation of silicide techniques limits the conditions of succeeding thermal processes. This limitation can be eliminated also by forming an interlayer insulating film by PECVD or single wafer processing type thermal CVD.
Formation of an interlayer insulating film by a low temperature process poses a problem of diffusion of moisture from the interlayer insulating film into a MOS transistor structure. An etch stopper (self-align contact (SAC)) is desired when a contact hole is etched through an interlayer insulating film to a source/drain region which uses silicide. To this end, technologies of forming a lamination structure of a thin nitride film and an oxide film formed on the nitride film, as an interlayer insulating film, have been developed in which both the nitride and oxide films are formed by PECVD or single wafer processing type thermal CVD or a combination of these CVD processes. The nitride film provides a moisture impermeable function and an etch stopper function.
Formation of an interlayer insulating film by PECVD or batch thermal CVD is associated with new problems such as an instable threshold voltage p-channel MOSFET and shortening of a lifetime of a p-channel MOSFET in terms of BT (bias temperature) stress and a lifetime of an n-channel MOSFET in terms of hot carriers. These problems become critical issues when high reliability semiconductor integrated circuit devices are to be manufactured.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a manufacture method of semiconductor devices capable of being fabricated finely and providing high reliability.
It is another object of the present invention to provide a manufacture method of semiconductor devices capable of being fabricated at low temperature processes and providing high reliability.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode; and depositing an insulating film covering the gate electrode over the semiconductor substrate, by parallel plate electrode plasma CVD using hydrogen-containing source gas under the conditions of a normalized RF power of 0.11 W/cm
2
to 0.85 W/cm
2
at the parallel plate electrode.
The insulating film covering the insulated gate electrode is deposited by plasma CVD with a limited RF power. Therefore, various problems associated with an insulating film formed by conventional batch thermal CVD or plasma CVD can be alleviated.
If an RF power is lowered, a film growth speed and film quality become bad. However, since the nitride film is not so thick and in a range of 20 nm to 100 nm (mostly, 50 nm to 70 nm), a low growth speed does not pose significant problems. Furthermore, since the nitride film as an etch stopper is not required to be strictly dense, the film quality does not cause much issue if the etching selection ratio is set sufficiently.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a MOS transistor structure on a semiconductor substrate, the MOS transistor structure having an insulated gate electrode; depositing a nitride film covering the insulated gate electrode on the said semiconductor substrate, by single wafer processing type thermal CVD; and depositing an oxide film on the nitride film by plasma CVD or single wafer processing type thermal CVD.
As an insulating film covering the gate electrode, a lamination structure is used which is made of a nitride film formed by single wafer processing type thermal CVD and an oxide film on the nitride film formed by plasma CVD or single wafer processing type thermal CVD. Therefore, various problems associated with an insulating film formed by conventional batch thermal CVD or plasma CVD can be alleviated.
As above, a semiconductor device having MOSFETs capable of satisfying the need of low temperature processes and providing high reliability can be manufactured.
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Japanese Office Action dated Feb. 13, 2001.
Ohta Hiroyuki
Satoh Hidekazu
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Quach T. N.
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