Low resistance, self-aligned, titanium silicide structures, usin

Details Low resistance, self-aligned, titanium silicide structures, usin Low resistance, self-aligned, titanium silicide structures, usin

1996-10-16

1998-04-28

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438592, 438694, 438683, H01L 21336

Patent

active

057443955

ABSTRACT:
A process for forming narrow polycide gate structures, using a low resistance, titanium silicide layer, has been developed. The process features initially forming a high resistance, titanium silicide layer, on exposed silicon regions, formed during the high temperature, PECVD titanium procedure. After deposition of a titanium nitride layer, used to protect the underlying high resistance, titanium silicide layer from a step RTA anneal is then used! to convert the high resistance titanium silicide layer to a lower resistance titanium silicide layer. A composite insulator spacer is also used to reduce possible metal, or silicide bridging phenomena.

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patent: 5322809 (1994-06-01), Moslehi
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patent: 5593924 (1997-01-01), Apte et al.
patent: 5665640 (1997-09-01), Foster et al.

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