Low power testing of very large circuits

Details Low power testing of very large circuits Low power testing of very large circuits

2003-01-06

2004-02-17

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06694467

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to reducing the power needed to test very large integrated and other circuits with serial and parallel scan paths and in particular relates to reducing the power required to perform these tests by dividing the scan paths into shorter scan paths and shifting each shorter scan path separately.
BACKGROUND
As transistor and interconnect geometry's shrink, the number of transistors capable of being connected together to form circuits in an integrated circuit (IC) increases. Also, the speed at which these circuits operate increases. With these increases in density and speed, the power consumed by circuits in an IC increases. The power consumed by an IC, according to the present invention, is of two general types, (1) the power consumed during functional operation of the IC, and (2) the power consumed during test operation of the IC. The functional operation power is the power consumed by the IC when it is operating in a system, such as a digital signal processor (DSP) IC operating in a cellular telephone. The test operation power is the power consumed by the IC when it is being tested, for example by a wafer or IC tester. In some instances, the test operation power may be much greater than the functional operation power.
According to the present invention, the test operation power is the power consumed by the IC or die when it is tested using the well known scan test methodology. As mentioned, the test operation power consumed during scan testing can be much greater than the functional operation power. This is because potentially all circuit registers (latches or DFFs), which are configured into scan cells, may be simultaneously clocked to shift data in and out during test. This differs from functional operation mode, where all circuit registers are not typically clocked simultaneously. In scan test mode, clocking all or near all circuit registers simultaneously causes the combinational logic connected to the registers to be dynamically activated. Dynamically activating the combinational logic during scan operations can cause the circuit to consume a significant amount of power.
SUMMARY OF THE INVENTION
The present invention provides a method of reducing the test operation power by improving upon the scan test methodology such that only portions of the scan circuitry are activated at any one time. By activating only portions of the overall scan circuitry, the power consumed during scan testing can be significantly reduced, especially in ICs designed with CMOS technology. Advantageously, the present invention achieves this lower power scan mode without increasing test time over the conventional scan test methodology. The improvements brought forth by the present invention can be applied in both single scan path test methodologies and in parallel scan path test methodologies. While the following description will teach the improvement as being incorporated in an IC, the improvement can be used at any level of circuit implementation. For example, intellectual property (IP) cores, which are predesigned subcircuits used to design highly complex system ICs, may themselves incorporate the improvement to lower their power consumption during test inside the system IC.


REFERENCES:
patent: 4947395 (1990-08-01), Bullinger et al.
patent: 5428622 (1995-06-01), Kuban et al.
patent: 402148147 (1990-06-01), None

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