Low CTE substrates for use with low-k flip-chip package devices

Details Low CTE substrates for use with low-k flip-chip package devices Low CTE substrates for use with low-k flip-chip package devices

2007-01-30

2007-01-30

Kebede, Brook (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE23003

Reexamination Certificate

active

11160753

ABSTRACT:
Disclosed are techniques that teach the replacement of the typical organic, plastic, or ceramic package substrate used in semiconductor package devices with a low-CTE package substrate. In one embodiment, a semiconductor device implementing the disclosed techniques is provided, where the device comprises an integrated circuit chip having at least one coupling component formed on an exterior surface thereof. Also, the device includes a package substrate having a mounting surface with bonding pads that are configured to receive the at least one coupling component. In such embodiments, the package substrate is selected or manufactured such that it has a coefficient of thermal expansion in a direction perpendicular to its mounting surface that is less than approximately twice a coefficient of thermal expansion along a plane parallel to its mounting surface.

REFERENCES:
patent: 6552267 (2003-04-01), Tsao et al.
patent: 6586322 (2003-07-01), Chiu et al.
patent: 6605524 (2003-08-01), Fan et al.
patent: 6855578 (2005-02-01), Odegard et al.
patent: 6888238 (2005-05-01), Li
patent: 2006/0079079 (2006-04-01), Muthukumar et al.

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